e-try.fit.eqn

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C1L27_cout_1 = C1_fre_N[8] & (!C1L24);
C1L27 = CARRY(C1L27_cout_1);


--C1_fre_N[9] is div:inst7|fre_N[9] at LC_X12_Y13_N2
--operation mode is arithmetic

C1_fre_N[9]_carry_eqn = (!C1L21 & C1L26) # (C1L21 & C1L27);
C1_fre_N[9]_lut_out = C1_fre_N[9] $ (C1_fre_N[9]_carry_eqn);
C1_fre_N[9] = DFFEAS(C1_fre_N[9]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L29 is div:inst7|fre_N[9]~452 at LC_X12_Y13_N2
--operation mode is arithmetic

C1L29_cout_0 = !C1L26 # !C1_fre_N[9];
C1L29 = CARRY(C1L29_cout_0);

--C1L30 is div:inst7|fre_N[9]~452COUT1_487 at LC_X12_Y13_N2
--operation mode is arithmetic

C1L30_cout_1 = !C1L27 # !C1_fre_N[9];
C1L30 = CARRY(C1L30_cout_1);


--C1_fre_N[10] is div:inst7|fre_N[10] at LC_X12_Y13_N3
--operation mode is arithmetic

C1_fre_N[10]_carry_eqn = (!C1L21 & C1L29) # (C1L21 & C1L30);
C1_fre_N[10]_lut_out = C1_fre_N[10] $ !C1_fre_N[10]_carry_eqn;
C1_fre_N[10] = DFFEAS(C1_fre_N[10]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L32 is div:inst7|fre_N[10]~456 at LC_X12_Y13_N3
--operation mode is arithmetic

C1L32_cout_0 = C1_fre_N[10] & !C1L29;
C1L32 = CARRY(C1L32_cout_0);

--C1L33 is div:inst7|fre_N[10]~456COUT1_488 at LC_X12_Y13_N3
--operation mode is arithmetic

C1L33_cout_1 = C1_fre_N[10] & !C1L30;
C1L33 = CARRY(C1L33_cout_1);


--C1L75 is div:inst7|LessThan~594 at LC_X11_Y14_N2
--operation mode is normal

C1L75 = !C1_fre_N[10] & !C1_fre_N[9] & !C1_fre_N[8] & !C1_fre_N[7];


--C1_fre_N[6] is div:inst7|fre_N[6] at LC_X12_Y14_N9
--operation mode is arithmetic

C1_fre_N[6]_carry_eqn = (!C1L7 & C1L18) # (C1L7 & C1L19);
C1_fre_N[6]_lut_out = C1_fre_N[6] $ (!C1_fre_N[6]_carry_eqn);
C1_fre_N[6] = DFFEAS(C1_fre_N[6]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L21 is div:inst7|fre_N[6]~460 at LC_X12_Y14_N9
--operation mode is arithmetic

C1L21 = CARRY(C1_fre_N[6] & (!C1L19));


--C1_fre_N[11] is div:inst7|fre_N[11] at LC_X12_Y13_N4
--operation mode is arithmetic

C1_fre_N[11]_carry_eqn = (!C1L21 & C1L32) # (C1L21 & C1L33);
C1_fre_N[11]_lut_out = C1_fre_N[11] $ C1_fre_N[11]_carry_eqn;
C1_fre_N[11] = DFFEAS(C1_fre_N[11]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L35 is div:inst7|fre_N[11]~464 at LC_X12_Y13_N4
--operation mode is arithmetic

C1L35 = CARRY(!C1L33 # !C1_fre_N[11]);


--C1_fre_N[12] is div:inst7|fre_N[12] at LC_X12_Y13_N5
--operation mode is arithmetic

C1_fre_N[12]_carry_eqn = C1L35;
C1_fre_N[12]_lut_out = C1_fre_N[12] $ !C1_fre_N[12]_carry_eqn;
C1_fre_N[12] = DFFEAS(C1_fre_N[12]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L37 is div:inst7|fre_N[12]~468 at LC_X12_Y13_N5
--operation mode is arithmetic

C1L37_cout_0 = C1_fre_N[12] & !C1L35;
C1L37 = CARRY(C1L37_cout_0);

--C1L38 is div:inst7|fre_N[12]~468COUT1_489 at LC_X12_Y13_N5
--operation mode is arithmetic

C1L38_cout_1 = C1_fre_N[12] & !C1L35;
C1L38 = CARRY(C1L38_cout_1);


--C1_fre_N[13] is div:inst7|fre_N[13] at LC_X12_Y13_N6
--operation mode is arithmetic

C1_fre_N[13]_carry_eqn = (!C1L35 & C1L37) # (C1L35 & C1L38);
C1_fre_N[13]_lut_out = C1_fre_N[13] $ (C1_fre_N[13]_carry_eqn);
C1_fre_N[13] = DFFEAS(C1_fre_N[13]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L40 is div:inst7|fre_N[13]~472 at LC_X12_Y13_N6
--operation mode is arithmetic

C1L40_cout_0 = !C1L37 # !C1_fre_N[13];
C1L40 = CARRY(C1L40_cout_0);

--C1L41 is div:inst7|fre_N[13]~472COUT1_490 at LC_X12_Y13_N6
--operation mode is arithmetic

C1L41_cout_1 = !C1L38 # !C1_fre_N[13];
C1L41 = CARRY(C1L41_cout_1);


--C1_fre_N[14] is div:inst7|fre_N[14] at LC_X12_Y13_N7
--operation mode is arithmetic

C1_fre_N[14]_carry_eqn = (!C1L35 & C1L40) # (C1L35 & C1L41);
C1_fre_N[14]_lut_out = C1_fre_N[14] $ (!C1_fre_N[14]_carry_eqn);
C1_fre_N[14] = DFFEAS(C1_fre_N[14]_lut_out, !GLOBAL(SYS_CLK), GLOBAL(SYS_RST_N), , , , , C1L79, );

--C1L43 is div:inst7|fre_N[14]~476 at LC_X12_Y13_N7
--operation mode is arithmetic

C1L43_cout_0 = C1_fre_N[14] & (!C1L40);
C1L43 = CARRY(C1L43_cout_0);

--C1L44 is div:inst7|fre_N[14]~476COUT1_491 at LC_X12_Y13_N7
--operation mode is arithmetic

C1L44_cout_1 = C1_fre_N[14] & (!C1L41);
C1L44 = CARRY(C1L44_cout_1);


--C1L76 is div:inst7|LessThan~595 at LC_X11_Y13_N2
--operation mode is normal

C1L76 = !C1_fre_N[13] # !C1_fre_N[12] # !C1_fre_N[11] # !C1_fre_N[14];


--C1L77 is div:inst7|LessThan~596 at LC_X12_Y14_N2
--operation mode is normal

C1L77 = C1L76 # C1L74 & C1L75 & !C1_fre_N[6];


--C1L78 is div:inst7|LessThan~597 at LC_X12_Y12_N8
--operation mode is normal

C1L78 = C1L72 # C1L77 & !C1_fre_N[17] & !C1_fre_N[15];


--C1L79 is div:inst7|LessThan~598 at LC_X12_Y12_N9
--operation mode is normal

C1L79 = C1_fre_N[24] & (C1_fre_N[23] # !C1L78 & !C1L71);


--B1_key_7279_tmp[7] is FPGA_7279:inst|key_7279_tmp[7] at LC_X42_Y18_N4
--operation mode is normal

B1_key_7279_tmp[7]_lut_out = B1L19 & (A1L8) # !B1L19 & B1_key_7279_tmp[7];
B1_key_7279_tmp[7] = DFFEAS(B1_key_7279_tmp[7]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_sdata_cnt[2] is FPGA_7279:inst|sdata_cnt[2] at LC_X42_Y17_N9
--operation mode is normal

B1_sdata_cnt[2]_lut_out = B1L67 & (B1_state.next_delay # B1_sdata_cnt[2] $ !B1L52) # !B1L67 & B1_sdata_cnt[2];
B1_sdata_cnt[2] = DFFEAS(B1_sdata_cnt[2]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_sdata_cnt[1] is FPGA_7279:inst|sdata_cnt[1] at LC_X43_Y16_N9
--operation mode is normal

B1_sdata_cnt[1]_lut_out = B1_state.next_delay # B1_sdata_cnt[1] $ !B1_sdata_cnt[0];
B1_sdata_cnt[1] = DFFEAS(B1_sdata_cnt[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L67, , , , );


--B1_sdata_cnt[0] is FPGA_7279:inst|sdata_cnt[0] at LC_X43_Y16_N0
--operation mode is normal

B1_sdata_cnt[0]_lut_out = B1_state.next_delay # !B1_sdata_cnt[0];
B1_sdata_cnt[0] = DFFEAS(B1_sdata_cnt[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L67, , , , );


--B1L52 is FPGA_7279:inst|LessThan~111 at LC_X42_Y17_N2
--operation mode is normal

B1L52 = B1_sdata_cnt[1] # B1_sdata_cnt[0];


--B1L42 is FPGA_7279:inst|key_7279[7]~54 at LC_X42_Y17_N3
--operation mode is normal

B1L42 = !B1_sdata_cnt[2] & B1_state.shift_key_high1 & !KEY7279 & !B1L52;


--B1_key_7279_tmp[6] is FPGA_7279:inst|key_7279_tmp[6] at LC_X42_Y18_N8
--operation mode is normal

B1_key_7279_tmp[6]_lut_out = B1L20 & (A1L8) # !B1L20 & (B1_key_7279_tmp[6]);
B1_key_7279_tmp[6] = DFFEAS(B1_key_7279_tmp[6]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[5] is FPGA_7279:inst|key_7279_tmp[5] at LC_X42_Y18_N3
--operation mode is normal

B1_key_7279_tmp[5]_lut_out = B1L21 & (A1L8) # !B1L21 & B1_key_7279_tmp[5];
B1_key_7279_tmp[5] = DFFEAS(B1_key_7279_tmp[5]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[4] is FPGA_7279:inst|key_7279_tmp[4] at LC_X41_Y17_N8
--operation mode is normal

B1_key_7279_tmp[4]_lut_out = B1L22 & (A1L8) # !B1L22 & B1_key_7279_tmp[4];
B1_key_7279_tmp[4] = DFFEAS(B1_key_7279_tmp[4]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[3] is FPGA_7279:inst|key_7279_tmp[3] at LC_X41_Y17_N7
--operation mode is normal

B1_key_7279_tmp[3]_lut_out = B1L23 & (A1L8) # !B1L23 & B1_key_7279_tmp[3];
B1_key_7279_tmp[3] = DFFEAS(B1_key_7279_tmp[3]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[2] is FPGA_7279:inst|key_7279_tmp[2] at LC_X41_Y17_N9
--operation mode is normal

B1_key_7279_tmp[2]_lut_out = B1L24 & (A1L8) # !B1L24 & (B1_key_7279_tmp[2]);
B1_key_7279_tmp[2] = DFFEAS(B1_key_7279_tmp[2]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[1] is FPGA_7279:inst|key_7279_tmp[1] at LC_X41_Y17_N2
--operation mode is normal

B1_key_7279_tmp[1]_lut_out = B1L25 & (A1L8) # !B1L25 & B1_key_7279_tmp[1];
B1_key_7279_tmp[1] = DFFEAS(B1_key_7279_tmp[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_key_7279_tmp[0] is FPGA_7279:inst|key_7279_tmp[0] at LC_X42_Y18_N7
--operation mode is normal

B1_key_7279_tmp[0]_lut_out = B1L26 & (A1L8) # !B1L26 & (B1_key_7279_tmp[0]);
B1_key_7279_tmp[0] = DFFEAS(B1_key_7279_tmp[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1L75 is FPGA_7279:inst|Select~1061 at LC_X43_Y17_N5
--operation mode is normal

B1L75 = !B1_sdata_cnt[2] & !B1L52 & (B1_state.shift_data_high # B1_state.shift_key_high1);


--B1_scmd_cnt[2] is FPGA_7279:inst|scmd_cnt[2] at LC_X44_Y16_N4
--operation mode is normal

B1_scmd_cnt[2]_lut_out = B1L62 & (B1L53 $ !B1_scmd_cnt[2] # !B1_state.shift_cmd_high) # !B1L62 & (B1_scmd_cnt[2]);
B1_scmd_cnt[2] = DFFEAS(B1_scmd_cnt[2]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1_scmd_cnt[1] is FPGA_7279:inst|scmd_cnt[1] at LC_X44_Y16_N7
--operation mode is normal

B1_scmd_cnt[1]_lut_out = B1_scmd_cnt[1] $ !B1_scmd_cnt[0] # !B1_state.shift_cmd_high;
B1_scmd_cnt[1] = DFFEAS(B1_scmd_cnt[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L62, , , , );


--B1_scmd_cnt[0] is FPGA_7279:inst|scmd_cnt[0] at LC_X44_Y16_N6
--operation mode is normal

B1_scmd_cnt[0]_lut_out = !B1_scmd_cnt[0] # !B1_state.shift_cmd_high;
B1_scmd_cnt[0] = DFFEAS(B1_scmd_cnt[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L62, , , , );


--B1L76 is FPGA_7279:inst|Select~1062 at LC_X43_Y17_N7
--operation mode is normal

B1L76 = !B1_scmd_cnt[2] & !B1_scmd_cnt[1] & !B1_scmd_cnt[0] & B1_state.shift_cmd_high;


--A1L21 is rtl~44 at LC_X44_Y17_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[2]_qfbk = B1_cmd_tmp1[2];
A1L21 = B1_cmd_tmp1[2]_qfbk & !B1_cmd_tmp1[7];

--B1_cmd_tmp1[2] is FPGA_7279:inst|cmd_tmp1[2] at LC_X44_Y17_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp1[2] = DFFEAS(A1L21, !GLOBAL(C2_clk_tmp), VCC, , B1L17, B1_cmd_tmp[2], , , VCC);


--B1L54 is FPGA_7279:inst|process0~0 at LC_X44_Y17_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_start_tmp_qfbk = B1_data_start_tmp;
B1L54 = B1_data_start_tmp_qfbk # B1_cmd_tmp1[0] & A1L21 & !B1_cmd_tmp1[1];

--B1_data_start_tmp is FPGA_7279:inst|data_start_tmp at LC_X44_Y17_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_data_start_tmp = DFFEAS(B1L54, !GLOBAL(C2_clk_tmp), VCC, , B1L17, B1_data_start, , , VCC);


--B1_delay_cnt[1] is FPGA_7279:inst|delay_cnt[1] at LC_X44_Y16_N9
--operation mode is normal

B1_delay_cnt[1]_lut_out = B1L32 & (B1_delay_cnt[1] $ !B1_delay_cnt[0] # !B1L57) # !B1L32 & B1_delay_cnt[1];
B1_delay_cnt[1] = DFFEAS(B1_delay_cnt[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , , , , , );


--B1L77 is FPGA_7279:inst|Select~1064 at LC_X44_Y16_N0
--operation mode is normal

B1L77 = !B1_delay_cnt[1] & (B1_state.start_delay);


--B1L53 is FPGA_7279:inst|LessThan~112 at LC_X44_Y16_N2
--operation mode is normal

B1L53 = B1_scmd_cnt[1] # B1_scmd_cnt[0];


--B1L78 is FPGA_7279:inst|Select~1065 at LC_X44_Y16_N5
--operation mode is normal

B1L78 = B1L77 # B1_state.shift_cmd_high & (B1L53 # B1_scmd_cnt[2]);

--B1_state.shift_cmd_low is FPGA_7279:inst|state.shift_cmd_low at LC_X44_Y16_N5
--operation mode is normal

B1_state.shift_cmd_low = DFFEAS(B1L78, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , , , , );


--B1L79 is FPGA_7279:inst|Select~1066 at LC_X43_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_data_high_qfbk = B1_state.shift_data_high;
B1L79 = B1_state.shift_data_high_qfbk & (B1_sdata_cnt[1] # B1_sdata_cnt[2] # B1_sdata_cnt[0]);

--B1_state.shift_data_high is FPGA_7279:inst|state.shift_data_high at LC_X43_Y16_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_state.shift_data_high = DFFEAS(B1L79, !GLOBAL(C2_clk_tmp), GLOBAL(SYS_RST_N), , , B1_state.shift_data_low, , , VCC);


--B1L80 is FPGA_7279:inst|Select~1067 at LC_X43_Y16_N2
--operation mode is normal

B1L80 = B1_state.next_delay & !B1_delay_cnt[1];


--B1_cmd_tmp[2] is FPGA_7279:inst|cmd_tmp[2] at LC_X43_Y17_N8
--operation mode is normal

B1_cmd_tmp[2]_lut_out = B1_seg_cnt[2] # !KEY7279;
B1_cmd_tmp[2] = DFFEAS(B1_cmd_tmp[2]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L12, , , , );


--B1_cmd_tmp[0] is FPGA_7279:inst|cmd_tmp[0] at LC_X43_Y18_N8
--operation mode is normal

B1_cmd_tmp[0]_lut_out = B1_seg_cnt[0] # !KEY7279;
B1_cmd_tmp[0] = DFFEAS(B1_cmd_tmp[0]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L12, , , , );


--B1_cmd_tmp[1] is FPGA_7279:inst|cmd_tmp[1] at LC_X43_Y18_N6
--operation mode is normal

B1_cmd_tmp[1]_lut_out = KEY7279 & B1_seg_cnt[1];
B1_cmd_tmp[1] = DFFEAS(B1_cmd_tmp[1]_lut_out, !GLOBAL(C2_clk_tmp), VCC, , B1L12, , , , );


--A1L22 is rtl~45 at LC_X43_Y17_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_cmd_tmp[7]_qfbk = B1_cmd_tmp[7];
A1L22 = B1_cmd_tmp[0] & !B1_cmd_tmp[1] & !B1_cmd_tmp[7]_qfbk & B1_cmd_tmp[2];

--B1_cmd_tmp[7] is FPGA_7279:inst|cmd_tmp[7] at LC_X43_Y17_N0