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parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES;
reg [width_a-1:0] tmp_buf;
reg [width_a-1:0] temp_result2;
initial
begin
// check if width_amount > 0
if (width_amount <= 0)
$display("Error! width_amount must be greater than 0.\n");
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
// check if width_a = width_o
if (width_a < width_o)
$display("Error! width_a must be greater than or equal to width_o.\n");
// check if width_o > 0
if (sgate_representation != 1 &&
sgate_representation != 0)
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
end
always @(a or amount or cin)
begin
tmp_buf[width_a-1:0]=a[width_a-1:0];
if (sgate_representation)
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = 1'b0;
end
else
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
temp_result2 = (tmp_buf << amount) | (ONES >> (width_a-amount)) ;
end
assign o = temp_result2[width_o-1:0];
endmodule // oper_left_shift
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_right_shift ( a, amount, cin, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_a-1:0] a;
input [width_amount-1:0] amount;
input cin;
output [width_o-1:0] o;
integer i;
reg [width_a-1:0] ONES;
reg [width_a-1:0] tmp_buf;
reg [width_a-1:0] temp_result2;
initial
begin
// check if width_amount > 0
if (width_amount <= 0)
$display("Error! width_amount must be greater than 0.\n");
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
// check if width_a = width_o
if (width_a < width_o)
$display("Error! width_a must be greater than or equal to width_o.\n");
// check if width_o > 0
if (sgate_representation != 1 &&
sgate_representation != 0)
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
end
always @(a or amount or cin)
begin
tmp_buf[width_a-1:0]=a[width_a-1:0];
if (sgate_representation)
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = 1'b1;
end
else
begin
for (i=0; i < width_a; i=i+1)
ONES[i] = cin;
end
if (a[width_a-1] == 0)
begin
temp_result2 = (tmp_buf >> amount);
end
else
begin
temp_result2 = (tmp_buf >> amount) | (ONES << (width_a-amount)) ;
end
end
assign o = temp_result2[width_o-1:0];
endmodule // oper_right_shift
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_rotate_left ( amount, a, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = 1'h0;
wire [width_a-1:0] result = temp_result[width_a-1:0];
lpm_clshift lpm_clshift_component (
.distance (amount),
.direction (temp_direction),
.data (a),
.result (temp_result),
.underflow (),
.overflow ()
);
defparam
lpm_clshift_component.lpm_type = "LPM_CLSHIFT",
lpm_clshift_component.lpm_shifttype = "ROTATE",
lpm_clshift_component.lpm_width = width_a,
lpm_clshift_component.lpm_widthdist = width_amount;
initial
begin
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
if (width_a != width_o)
$display("Error! width_a must be equal to width_o.\n");
if (sgate_representation != 1 &&
sgate_representation != 0)
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
end
endmodule //oper_rotate_left
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_rotate_right ( amount, a, o);
parameter width_a = 6;
parameter width_amount = 6;
parameter width_o = 6;
parameter sgate_representation = 0;
input [width_amount-1:0] amount;
input [width_a-1:0] a;
output [width_o-1:0] o;
wire [width_a-1:0] temp_result;
wire temp_direction = 1'h1;
wire [width_a-1:0] result = temp_result[width_a-1:0];
lpm_clshift lpm_clshift_component (
.distance (amount),
.direction (temp_direction),
.data (a),
.result (temp_result),
.underflow (),
.overflow ()
);
defparam
lpm_clshift_component.lpm_type = "LPM_CLSHIFT",
lpm_clshift_component.lpm_shifttype = "ROTATE",
lpm_clshift_component.lpm_width = width_a,
lpm_clshift_component.lpm_widthdist = width_amount;
initial
begin
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
if (width_a != width_o)
$display("Error! width_a must be equal to width_o.\n");
if (sgate_representation != 1 &&
sgate_representation != 0)
$display("Error! sgate_representation value must be 1 (SIGNED) or 0 (UNSIGNED).");
end
endmodule //oper_rotate_right
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_less_than (a, b, cin, o);
parameter width_a = 6;
parameter width_b = 6;
parameter sgate_representation = 0;
parameter width_max= width_a>width_b ? width_a : width_b;
input [width_a-1:0] a;
input [width_b-1:0] b;
input cin;
output o;
integer sa;
integer sb;
reg [width_a-1:0] not_a;
reg [width_b-1:0] not_b;
reg tmp_result;
initial
begin
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_datain must be greater than 0.\n");
if (width_b <= 0)
$display("Error! width_datain must be greater than 0.\n");
end
always @(a or b or cin)
begin
sa = a;
sb = b;
not_a = ~a;
not_b = ~b;
if (sgate_representation == "SIGNED")
begin
if (a[width_a-1] == 1)
sa = (not_a) * (-1) - 1;
if (b[width_b-1] == 1)
sb = (not_b) * (-1) - 1;
if (sa<sb)
begin
tmp_result = 1;
end
else if ((sa==sb)&&(cin))
begin
tmp_result = 1;
end
else
begin
tmp_result = 0;
end
end
else
begin
if (a<b)
begin
tmp_result = 1;
end
else if ((a==b)&&(cin))
begin
tmp_result = 1;
end
else
begin
tmp_result = 0;
end
end
end
assign o = tmp_result;
endmodule // oper_less_than
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_mux ( sel, data, o);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
initial
begin
temp_result = 'bz;
// check if width_a > 0
if (width_data <= 0)
$display("Error! width_data must be greater than 0.\n");
// check if width_b > 0
if (width_sel <= 0)
$display("Error! width_sel must be greater than 0.\n");
// check if width_o > 0
end
always @(data or sel)
begin
temp_result = data[sel];
end
assign o = temp_result;
endmodule //oper_mux
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_selector ( sel, data, o);
parameter width_sel = 6;
parameter width_data = 6;
input [width_sel-1:0] sel;
input [width_data-1:0] data;
output o;
reg temp_result;
reg [width_data-1:0] result;
integer i;
initial
begin
// check if width_a > 0
if (width_sel <= 0)
$display("Error! width_sel must be greater than 0.\n");
if (width_data != width_sel)
$display("Error! width_sel must be equal to width_data.\n");
end
always @(data or sel)
begin
temp_result = 1'b0;
for (i = 0; i < width_sel; i = i + 1)
if (sel[i] == 1)
begin
temp_result= temp_result | data[i];
end
end
assign o = temp_result;
endmodule //oper_selector
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_decoder ( i, o);
parameter width_i = 6;
parameter width_o = 6;
input [width_i-1:0] i;
output [width_o-1:0] o;
initial
begin
// check if width_i > 0
if (width_i <= 0)
$display("Error! width_i must be greater than 0.\n");
if (width_o <= 0)
$display("Error! width_o must be greater than 0.\n");
end
lpm_decode lpm_decode_component (
.data (i),
.eq (o),
.enable (),
.clock (),
.aclr (),
.clken ()
);
defparam
lpm_decode_component.lpm_width = width_i,
lpm_decode_component.lpm_decodes = width_o,
lpm_decode_component.lpm_type = "LPM_DECODE";
endmodule //oper_decoder
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module oper_bus_mux ( a, b, sel, o);
parameter width_a = 6;
parameter width_b = 6;
parameter width_o = 6;
input [width_a-1:0] a;
input [width_b-1:0] b;
input sel;
output [width_o-1:0] o;
wire [width_a+width_b-1:0] all_inps;
assign all_inps[width_a-1:0]=a[width_a-1:0];
assign all_inps[width_a+width_b-1:width_a]=b[width_b-1:0];
initial
begin
// check if width_a > 0
if (width_a <= 0)
$display("Error! width_a must be greater than 0.\n");
if (width_b <= 0)
$display("Error! width_o must be greater than 0.\n");
if (width_a != width_b)
$display("Error! width_a must equal width_b.\n");
if (width_a != width_o)
$display("Error! width_a must equal width_o.\n");
end
lpm_mux lpm_mux_component (
.data (all_inps),
.sel(sel),
.result (o),
.clock (),
.aclr (),
.clken ()
);
defparam
lpm_mux_component.lpm_width = width_o,
lpm_mux_component.lpm_size = 2,
lpm_mux_component.lpm_widths = 1,
lpm_mux_component.lpm_type = "lpm_mux";
endmodule //oper_bus_mux
////------------------------------------------------------------------------------------------
////------------------------------------------------------------------------------------------
`timescale 1 ps / 1ps
module latch(datain, dataout, latch_enable);
input datain, latch_enable;
output dataout;
reg dataout;
always @(datain or latch_enable)
begin
if (latch_enable)
dataout = datain;
end
endmodule //latch
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