uart_regs.fit.eqn

uart_regs core目录下为Altera的IP宏功能模块

M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[3] = M1_q_b[0]_PORT_B_data_out[3];

--M1_q_b[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[2] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[2] = M1_q_b[0]_PORT_B_data_out[2];

--M1_q_b[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|q_b[1] at M512_X26_Y27
M1_q_b[0]_PORT_A_data_in = BUS(C1_rf_data_in[0], C1_rf_data_in[1], C1_rf_data_in[2], C1_rf_data_in[3], C1_rf_data_in[4], C1_rf_data_in[5], C1_rf_data_in[6], C1_rf_data_in[7], C1_rf_data_in[8], C1_rf_data_in[9]);
M1_q_b[0]_PORT_A_data_in_reg = DFFE(M1_q_b[0]_PORT_A_data_in, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_A_address = BUS(E4_safe_q[0], E4_safe_q[1], E4_safe_q[2], E4_safe_q[3]);
M1_q_b[0]_PORT_A_address_reg = DFFE(M1_q_b[0]_PORT_A_address, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_address = BUS(E3_safe_q[0], E3_safe_q[1], E3_safe_q[2], E3_safe_q[3]);
M1_q_b[0]_PORT_B_address_reg = DFFE(M1_q_b[0]_PORT_B_address, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_PORT_A_write_enable = J1L2;
M1_q_b[0]_PORT_A_write_enable_reg = DFFE(M1_q_b[0]_PORT_A_write_enable, M1_q_b[0]_clock_0, , , );
M1_q_b[0]_PORT_B_read_enable = VCC;
M1_q_b[0]_PORT_B_read_enable_reg = DFFE(M1_q_b[0]_PORT_B_read_enable, M1_q_b[0]_clock_1, , , M1_q_b[0]_clock_enable_1);
M1_q_b[0]_clock_0 = GLOBAL(clk);
M1_q_b[0]_clock_1 = GLOBAL(clk);
M1_q_b[0]_clock_enable_1 = J1L1;
M1_q_b[0]_PORT_B_data_out = MEMORY(M1_q_b[0]_PORT_A_data_in_reg, , M1_q_b[0]_PORT_A_address_reg, M1_q_b[0]_PORT_B_address_reg, M1_q_b[0]_PORT_A_write_enable_reg, M1_q_b[0]_PORT_B_read_enable_reg, , , M1_q_b[0]_clock_0, M1_q_b[0]_clock_1, , M1_q_b[0]_clock_enable_1, , );
M1_q_b[1] = M1_q_b[0]_PORT_B_data_out[1];


--E2_safe_q[3] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X23_Y28_N4
--operation mode is normal

E2_safe_q[3]_lut_out = E2_safe_q[3] $ E2L81;
E2_safe_q[3] = DFFEA(E2_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , K1L1, , );


--E2_safe_q[2] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X23_Y28_N3
--operation mode is arithmetic

E2_safe_q[2]_lut_out = E2_safe_q[2] $ !E2L51;
E2_safe_q[2] = DFFEA(E2_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , K1L1, , );

--E2L81 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X23_Y28_N3
--operation mode is arithmetic

E2L81_cout_0 = !E2L51 & (E2_safe_q[2] $ !J1L2);
E2L81 = CARRY(E2L81_cout_0);

--E2L91 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X23_Y28_N3
--operation mode is arithmetic

E2L91_cout_1 = !E2L61 & (E2_safe_q[2] $ !J1L2);
E2L91 = CARRY(E2L91_cout_1);


--E2_safe_q[1] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X23_Y28_N2
--operation mode is arithmetic

E2_safe_q[1]_lut_out = E2_safe_q[1] $ E2L21;
E2_safe_q[1] = DFFEA(E2_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , K1L1, , );

--E2L51 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X23_Y28_N2
--operation mode is arithmetic

E2L51_cout_0 = E2_safe_q[1] $ J1L2 # !E2L21;
E2L51 = CARRY(E2L51_cout_0);

--E2L61 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X23_Y28_N2
--operation mode is arithmetic

E2L61_cout_1 = E2_safe_q[1] $ J1L2 # !E2L31;
E2L61 = CARRY(E2L61_cout_1);


--E2_safe_q[0] is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X23_Y28_N1
--operation mode is arithmetic

E2_safe_q[0]_lut_out = !E2_safe_q[0];
E2_safe_q[0] = DFFEA(E2_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(C1L96), , K1L1, , );

--E2L21 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X23_Y28_N1
--operation mode is arithmetic

E2L21_cout_0 = E2_safe_q[0] $ !J1L2;
E2L21 = CARRY(E2L21_cout_0);

--E2L31 is uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X23_Y28_N1
--operation mode is arithmetic

E2L31_cout_1 = E2_safe_q[0] $ !J1L2;
E2L31 = CARRY(E2L31_cout_1);


--E7_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X3_Y24_N9
--operation mode is normal

E7_safe_q[3]_lut_out = E7_safe_q[3] $ (E7L71 & K2L9);
E7_safe_q[3] = DFFEA(E7_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );


--E7_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X3_Y24_N8
--operation mode is arithmetic

E7_safe_q[2]_lut_out = E7_safe_q[2] $ (K2L9 & !E7L41);
E7_safe_q[2] = DFFEA(E7_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E7L71 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X3_Y24_N8
--operation mode is arithmetic

E7L71_cout_0 = E7_safe_q[2] & !E7L41;
E7L71 = CARRY(E7L71_cout_0);

--E7L81 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X3_Y24_N8
--operation mode is arithmetic

E7L81_cout_1 = E7_safe_q[2] & !E7L51;
E7L81 = CARRY(E7L81_cout_1);


--E7_safe_q[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X3_Y24_N7
--operation mode is arithmetic

E7_safe_q[1]_lut_out = E7_safe_q[1] $ (K2L9 & E7L11);
E7_safe_q[1] = DFFEA(E7_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E7L41 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X3_Y24_N7
--operation mode is arithmetic

E7L41_cout_0 = !E7L11 # !E7_safe_q[1];
E7L41 = CARRY(E7L41_cout_0);

--E7L51 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X3_Y24_N7
--operation mode is arithmetic

E7L51_cout_1 = !E7L21 # !E7_safe_q[1];
E7L51 = CARRY(E7L51_cout_1);


--E7_safe_q[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X3_Y24_N6
--operation mode is arithmetic

E7_safe_q[0]_lut_out = E7_safe_q[0] $ K2L9;
E7_safe_q[0] = DFFEA(E7_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E7L11 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X3_Y24_N6
--operation mode is arithmetic

E7L11_cout_0 = E7_safe_q[0];
E7L11 = CARRY(E7L11_cout_0);

--E7L21 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:wr_ptr|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X3_Y24_N6
--operation mode is arithmetic

E7L21_cout_1 = E7_safe_q[0];
E7L21 = CARRY(E7L21_cout_1);


--E6_safe_q[3] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[3] at LC_X3_Y24_N4
--operation mode is normal

E6_safe_q[3]_lut_out = E6_safe_q[3] $ (K2_valid_rreq & E6L71);
E6_safe_q[3] = DFFEA(E6_safe_q[3]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );


--E6_safe_q[2] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2] at LC_X3_Y24_N3
--operation mode is arithmetic

E6_safe_q[2]_lut_out = E6_safe_q[2] $ (K2_valid_rreq & !E6L41);
E6_safe_q[2] = DFFEA(E6_safe_q[2]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E6L71 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT0 at LC_X3_Y24_N3
--operation mode is arithmetic

E6L71_cout_0 = E6_safe_q[2] & !E6L41;
E6L71 = CARRY(E6L71_cout_0);

--E6L81 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[2]~COUT1 at LC_X3_Y24_N3
--operation mode is arithmetic

E6L81_cout_1 = E6_safe_q[2] & !E6L51;
E6L81 = CARRY(E6L81_cout_1);


--E6_safe_q[1] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1] at LC_X3_Y24_N2
--operation mode is arithmetic

E6_safe_q[1]_lut_out = E6_safe_q[1] $ (K2_valid_rreq & E6L11);
E6_safe_q[1] = DFFEA(E6_safe_q[1]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E6L41 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT0 at LC_X3_Y24_N2
--operation mode is arithmetic

E6L41_cout_0 = !E6L11 # !E6_safe_q[1];
E6L41 = CARRY(E6L41_cout_0);

--E6L51 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[1]~COUT1 at LC_X3_Y24_N2
--operation mode is arithmetic

E6L51_cout_1 = !E6L21 # !E6_safe_q[1];
E6L51 = CARRY(E6L51_cout_1);


--E6_safe_q[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X3_Y24_N1
--operation mode is arithmetic

E6_safe_q[0]_lut_out = E6_safe_q[0] $ K2_valid_rreq;
E6_safe_q[0] = DFFEA(E6_safe_q[0]_lut_out, GLOBAL(clk), !GLOBAL(D1_i12), , , , );

--E6L11 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X3_Y24_N1
--operation mode is arithmetic

E6L11_cout_0 = E6_safe_q[0];
E6L11 = CARRY(E6L11_cout_0);

--E6L21 is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|lpm_counter:rd_ptr_count|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X3_Y24_N1
--operation mode is arithmetic

E6L21_cout_1 = E6_safe_q[0];
E6L21 = CARRY(E6L21_cout_1);


--S1_q_b[0] is uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|q_b[0] at M512_X4_Y24
S1_q_b[0]_PORT_A_data_in = BUS(wb_dat_i[0], wb_dat_i[1], wb_dat_i[2], wb_dat_i[3], wb_dat_i[4], wb_dat_i[5], wb_dat_i[6], wb_dat_i[7]);
S1_q_b[0]_PORT_A_data_in_reg = DFFE(S1_q_b[0]_PORT_A_data_in, S1_q_b[0]_clock_0, , , );
S1_q_b[0]_PORT_A_address = BUS(E7_safe_q[0], E7_safe_q[1], E7_safe_q[2], E7_safe_q[3]);
S1_q_b[0]_PORT_A_address_reg = DFFE(S1_q_b[0]_PORT_A_address, S1_q_b[0]_clock_0, , , );