📄 uart_regs.tan.rpt
字号:
; Clock Setup: 'clk' ; 2.602 ns ; 130.01 MHz ( period = 7.692 ns ) ; 196.46 MHz ( period = 5.090 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 ; uart_transmitter:transmitter|parity_xor ;
; Clock Setup: 'wb_we_i' ; N/A ; None ; 326.16 MHz ( period = 3.066 ns ) ; lcr[7] ; dl[0] ;
+------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; clk ; User Pin ; 130.01 MHz ; NONE ; N/A ; N/A ; N/A ;
; wb_we_i ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 2.602 ns ; 196.46 MHz ( period = 5.090 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg3 ; uart_transmitter:transmitter|parity_xor ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.738 ns ;
; 2.602 ns ; 196.46 MHz ( period = 5.090 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg2 ; uart_transmitter:transmitter|parity_xor ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.738 ns ;
; 2.602 ns ; 196.46 MHz ( period = 5.090 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg1 ; uart_transmitter:transmitter|parity_xor ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.738 ns ;
; 2.602 ns ; 196.46 MHz ( period = 5.090 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|dpram_81k:FIFOram|altsyncram_mmb1:altsyncram1|ram_block2a0~portb_address_reg0 ; uart_transmitter:transmitter|parity_xor ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.738 ns ;
; 3.107 ns ; 218.10 MHz ( period = 4.585 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[3] ; lsr6_d ; clk ; clk ; 7.692 ns ; 7.471 ns ; 4.364 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[14] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[12] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[13] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[11] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[10] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[9] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.128 ns ; 219.11 MHz ( period = 4.564 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[8] ; clk ; clk ; 7.692 ns ; 7.506 ns ; 4.378 ns ;
; 3.132 ns ; 219.30 MHz ( period = 4.560 ns ) ; uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg3 ; lsr7r ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.208 ns ;
; 3.132 ns ; 219.30 MHz ( period = 4.560 ns ) ; uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg2 ; lsr7r ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.208 ns ;
; 3.132 ns ; 219.30 MHz ( period = 4.560 ns ) ; uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg1 ; lsr7r ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.208 ns ;
; 3.132 ns ; 219.30 MHz ( period = 4.560 ns ) ; uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg0 ; lsr7r ; clk ; clk ; 7.692 ns ; 7.340 ns ; 4.208 ns ;
; 3.230 ns ; 224.11 MHz ( period = 4.462 ns ) ; uart_transmitter:transmitter|myfifo_8:myfifo_u1|scfifo:scfifo_component|scfifo_eaq:auto_generated|a_dpfifo_rll:dpfifo|a_fefifo_qve:fifo_state|lpm_counter:count_usedw|alt_counter_stratix:wysi_counter|safe_q[0] ; lsr6_d ; clk ; clk ; 7.692 ns ; 7.471 ns ; 4.241 ns ;
; 3.237 ns ; 224.47 MHz ( period = 4.455 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[15] ; clk ; clk ; 7.692 ns ; 7.504 ns ; 4.267 ns ;
; 3.237 ns ; 224.47 MHz ( period = 4.455 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[14] ; clk ; clk ; 7.692 ns ; 7.504 ns ; 4.267 ns ;
; 3.237 ns ; 224.47 MHz ( period = 4.455 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[12] ; clk ; clk ; 7.692 ns ; 7.504 ns ; 4.267 ns ;
; 3.237 ns ; 224.47 MHz ( period = 4.455 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[13] ; clk ; clk ; 7.692 ns ; 7.504 ns ; 4.267 ns ;
; 3.237 ns ; 224.47 MHz ( period = 4.455 ns ) ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3] ; lpm_counter:dlc_rtl_0|alt_counter_stratix:wysi_counter|safe_q[11] ; clk ; clk ; 7.692 ns ; 7.504 ns ; 4.267 ns ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -