uart_regs.tan.rpt

uart_regs core目录下为Altera的IP宏功能模块

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+-------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                    ;
+--------------------------------------------------------------------------------------------------------------
; Option                                                           ; Setting            ; From    ; To        ;
+------------------------------------------------------------------+--------------------+---------+-----------+
; Device name                                                      ; EP1S10B672C6       ;         ;           ;
; Report IO Paths Separately                                       ; Off                ;         ;           ;
; Include external delays to/from device pins in fmax calculations ; Off                ;         ;           ;
; Ignore user-defined clock settings                               ; Off                ;         ;           ;
; Default hold multicycle                                          ; Same as Multicycle ;         ;           ;
; Cut off feedback from I/O pins                                   ; On                 ;         ;           ;
; Cut off clear and preset signal paths                            ; On                 ;         ;           ;
; Cut off read during write signal paths                           ; On                 ;         ;           ;
; Cut paths between unrelated clock domains                        ; On                 ;         ;           ;
; Run Minimum Analysis                                             ; On                 ;         ;           ;
; Use Minimum Timing Models                                        ; Off                ;         ;           ;
; Number of paths to report                                        ; 200                ;         ;           ;
; Number of destination nodes to report                            ; 10                 ;         ;           ;
; Number of source nodes to report per destination node            ; 10                 ;         ;           ;
; Clock Settings                                                   ; clk                ;         ; clk       ;
; tsu Requirement                                                  ; 12ns               ; wb_we_i ; wb_addr_i ;
; th Requirement                                                   ; 3ns                ; wb_we_i ; wb_addr_i ;
+------------------------------------------------------------------+--------------------+---------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                 ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type                   ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                                                ; To                                      ;
+------------------------+----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+
; Worst-case tsu         ; 8.989 ns ; 12.000 ns                        ; 3.011 ns                         ; wb_addr_i[2]                                                                                                                                                                                        ; scratch[2]                              ;
; Worst-case tco         ; N/A      ; None                             ; 18.054 ns                        ; uart_receiver:receiver|myfifo_10:myfifo_u|scfifo:scfifo_component|scfifo_nbq:auto_generated|a_dpfifo_4nl:dpfifo|dpram_h2k:FIFOram|altsyncram_apb1:altsyncram1|ram_block2a0~portb_address_reg3       ; wb_dat_o[0]                             ;
; Worst-case tpd         ; N/A      ; None                             ; 15.420 ns                        ; wb_addr_i[0]                                                                                                                                                                                        ; wb_dat_o[0]                             ;
; Worst-case th          ; 3.465 ns ; 3.000 ns                         ; -0.465 ns                        ; wb_addr_i[0]                                                                                                                                                                                        ; start_dlc                               ;
; Worst-case minimum tco ; N/A      ; None                             ; 8.502 ns                         ; int_o~reg0                                                                                                                                                                                          ; int_o                                   ;
; Worst-case minimum tpd ; N/A      ; None                             ; 10.597 ns                        ; wb_addr_i[0]                                                                                                                                                                                        ; wb_dat_o[5]                             ;