sum32.tan.qmsg

利用EDA硬件描述语言来实现DDS功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register temp\[2\] temp\[31\] 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"temp\[2\]\" and destination register \"temp\[31\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.179 ns + Longest register register " "Info: + Longest register to register delay is 3.179 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[2\] 1 REG LC_X34_Y16_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y16_N6; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[2] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns temp\[2\]~1066COUT1_1098 2 COMB LC_X34_Y16_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X34_Y16_N6; Fanout = 2; COMB Node = 'temp\[2\]~1066COUT1_1098'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.098 ns" { temp[2] temp[2]~1066COUT1_1098 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns temp\[3\]~1067COUT1_1099 3 COMB LC_X34_Y16_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X34_Y16_N7; Fanout = 2; COMB Node = 'temp\[3\]~1067COUT1_1099'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns temp\[4\]~1068COUT1_1100 4 COMB LC_X34_Y16_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X34_Y16_N8; Fanout = 2; COMB Node = 'temp\[4\]~1068COUT1_1100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns temp\[5\]~1069 5 COMB LC_X34_Y16_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X34_Y16_N9; Fanout = 6; COMB Node = 'temp\[5\]~1069'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { temp[4]~1068COUT1_1100 temp[5]~1069 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns temp\[10\]~1074 6 COMB LC_X34_Y15_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X34_Y15_N4; Fanout = 6; COMB Node = 'temp\[10\]~1074'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[5]~1069 temp[10]~1074 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.860 ns temp\[15\]~1079 7 COMB LC_X34_Y15_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 1.860 ns; Loc. = LC_X34_Y15_N9; Fanout = 6; COMB Node = 'temp\[15\]~1079'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { temp[10]~1074 temp[15]~1079 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.996 ns temp\[20\]~1084 8 COMB LC_X34_Y14_N4 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.996 ns; Loc. = LC_X34_Y14_N4; Fanout = 6; COMB Node = 'temp\[20\]~1084'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[15]~1079 temp[20]~1084 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.204 ns temp\[25\]~1089 9 COMB LC_X34_Y14_N9 6 " "Info: 9: + IC(0.000 ns) + CELL(0.208 ns) = 2.204 ns; Loc. = LC_X34_Y14_N9; Fanout = 6; COMB Node = 'temp\[25\]~1089'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { temp[20]~1084 temp[25]~1089 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.340 ns temp\[30\]~1094 10 COMB LC_X34_Y13_N4 1 " "Info: 10: + IC(0.000 ns) + CELL(0.136 ns) = 2.340 ns; Loc. = LC_X34_Y13_N4; Fanout = 1; COMB Node = 'temp\[30\]~1094'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[25]~1089 temp[30]~1094 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.179 ns temp\[31\] 11 REG LC_X34_Y13_N5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.839 ns) = 3.179 ns; Loc. = LC_X34_Y13_N5; Fanout = 2; REG Node = 'temp\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { temp[30]~1094 temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.656 ns ( 83.55 % ) " "Info: Total cell delay = 2.656 ns ( 83.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.523 ns ( 16.45 % ) " "Info: Total interconnect delay = 0.523 ns ( 16.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.179 ns" { temp[2] temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 temp[5]~1069 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.179 ns" { temp[2] temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 temp[5]~1069 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns temp\[31\] 2 REG LC_X34_Y13_N5 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X34_Y13_N5; Fanout = 2; REG Node = 'temp\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[31] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns temp\[2\] 2 REG LC_X34_Y16_N6 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X34_Y16_N6; Fanout = 4; REG Node = 'temp\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk temp[2] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[2] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[31] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[2] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.179 ns" { temp[2] temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 temp[5]~1069 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.179 ns" { temp[2] temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 temp[5]~1069 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[31] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[2] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { temp[31] } {  } {  } } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "temp\[31\] k\[10\] clk 8.464 ns register " "Info: tsu for register \"temp\[31\]\" (data pin = \"k\[10\]\", clock pin = \"clk\") is 8.464 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.389 ns + Longest pin register " "Info: + Longest pin to register delay is 11.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns k\[10\] 1 PIN PIN_17 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 2; PIN Node = 'k\[10\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { k[10] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.675 ns) + CELL(0.718 ns) 9.862 ns temp\[10\]~1074 2 COMB LC_X34_Y15_N4 6 " "Info: 2: + IC(7.675 ns) + CELL(0.718 ns) = 9.862 ns; Loc. = LC_X34_Y15_N4; Fanout = 6; COMB Node = 'temp\[10\]~1074'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.393 ns" { k[10] temp[10]~1074 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 10.070 ns temp\[15\]~1079 3 COMB LC_X34_Y15_N9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.208 ns) = 10.070 ns; Loc. = LC_X34_Y15_N9; Fanout = 6; COMB Node = 'temp\[15\]~1079'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { temp[10]~1074 temp[15]~1079 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.206 ns temp\[20\]~1084 4 COMB LC_X34_Y14_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.136 ns) = 10.206 ns; Loc. = LC_X34_Y14_N4; Fanout = 6; COMB Node = 'temp\[20\]~1084'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[15]~1079 temp[20]~1084 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 10.414 ns temp\[25\]~1089 5 COMB LC_X34_Y14_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 10.414 ns; Loc. = LC_X34_Y14_N9; Fanout = 6; COMB Node = 'temp\[25\]~1089'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { temp[20]~1084 temp[25]~1089 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.550 ns temp\[30\]~1094 6 COMB LC_X34_Y13_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 10.550 ns; Loc. = LC_X34_Y13_N4; Fanout = 1; COMB Node = 'temp\[30\]~1094'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[25]~1089 temp[30]~1094 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.389 ns temp\[31\] 7 REG LC_X34_Y13_N5 2 " "Info: 7: + IC(0.000 ns) + CELL(0.839 ns) = 11.389 ns; Loc. = LC_X34_Y13_N5; Fanout = 2; REG Node = 'temp\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { temp[30]~1094 temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.714 ns ( 32.61 % ) " "Info: Total cell delay = 3.714 ns ( 32.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.675 ns ( 67.39 % ) " "Info: Total interconnect delay = 7.675 ns ( 67.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.389 ns" { k[10] temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.389 ns" { k[10] k[10]~out0 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } { 0.000ns 0.000ns 7.675ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.718ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns temp\[31\] 2 REG LC_X34_Y13_N5 2 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X34_Y13_N5; Fanout = 2; REG Node = 'temp\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[31] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.389 ns" { k[10] temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.389 ns" { k[10] k[10]~out0 temp[10]~1074 temp[15]~1079 temp[20]~1084 temp[25]~1089 temp[30]~1094 temp[31] } { 0.000ns 0.000ns 7.675ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.718ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[31] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out1\[12\] temp\[12\] 9.487 ns register " "Info: tco from clock \"clk\" to destination pin \"out1\[12\]\" through register \"temp\[12\]\" is 9.487 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns temp\[12\] 2 REG LC_X34_Y15_N6 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X34_Y15_N6; Fanout = 4; REG Node = 'temp\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk temp[12] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[12] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.301 ns + Longest register pin " "Info: + Longest register to pin delay is 6.301 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[12\] 1 REG LC_X34_Y15_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y15_N6; Fanout = 4; REG Node = 'temp\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[12] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.177 ns) + CELL(2.124 ns) 6.301 ns out1\[12\] 2 PIN PIN_18 0 " "Info: 2: + IC(4.177 ns) + CELL(2.124 ns) = 6.301 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'out1\[12\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.301 ns" { temp[12] out1[12] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 33.71 % ) " "Info: Total cell delay = 2.124 ns ( 33.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.177 ns ( 66.29 % ) " "Info: Total interconnect delay = 4.177 ns ( 66.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.301 ns" { temp[12] out1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.301 ns" { temp[12] out1[12] } { 0.000ns 4.177ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[12] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.301 ns" { temp[12] out1[12] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.301 ns" { temp[12] out1[12] } { 0.000ns 4.177ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "temp\[19\] k\[19\] clk -1.257 ns register " "Info: th for register \"temp\[19\]\" (data pin = \"k\[19\]\", clock pin = \"clk\") is -1.257 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.962 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 32 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns temp\[19\] 2 REG LC_X34_Y14_N3 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X34_Y14_N3; Fanout = 4; REG Node = 'temp\[19\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.493 ns" { clk temp[19] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[19] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.234 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns k\[19\] 1 PIN PIN_152 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_152; Fanout = 3; PIN Node = 'k\[19\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { k[19] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.027 ns) + CELL(0.738 ns) 4.234 ns temp\[19\] 2 REG LC_X34_Y14_N3 4 " "Info: 2: + IC(2.027 ns) + CELL(0.738 ns) = 4.234 ns; Loc. = LC_X34_Y14_N3; Fanout = 4; REG Node = 'temp\[19\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.765 ns" { k[19] temp[19] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 52.13 % ) " "Info: Total cell delay = 2.207 ns ( 52.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.027 ns ( 47.87 % ) " "Info: Total interconnect delay = 2.027 ns ( 47.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.234 ns" { k[19] temp[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.234 ns" { k[19] k[19]~out0 temp[19] } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.962 ns" { clk temp[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.962 ns" { clk clk~out0 temp[19] } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.234 ns" { k[19] temp[19] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.234 ns" { k[19] k[19]~out0 temp[19] } { 0.000ns 0.000ns 2.027ns } { 0.000ns 1.469ns 0.738ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}