sum32.fit.qmsg

利用EDA硬件描述语言来实现DDS功能

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.116 ns register register " "Info: Estimated most critical path is register to register delay of 3.116 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns temp\[1\] 1 REG LAB_X34_Y16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X34_Y16; Fanout = 4; REG Node = 'temp\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { temp[1] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.608 ns) + CELL(0.432 ns) 1.040 ns temp\[1\]~1065COUT1_1097 2 COMB LAB_X34_Y16 2 " "Info: 2: + IC(0.608 ns) + CELL(0.432 ns) = 1.040 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'temp\[1\]~1065COUT1_1097'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.040 ns" { temp[1] temp[1]~1065COUT1_1097 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.120 ns temp\[2\]~1066COUT1_1098 3 COMB LAB_X34_Y16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.120 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'temp\[2\]~1066COUT1_1098'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { temp[1]~1065COUT1_1097 temp[2]~1066COUT1_1098 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.200 ns temp\[3\]~1067COUT1_1099 4 COMB LAB_X34_Y16 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.200 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'temp\[3\]~1067COUT1_1099'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { temp[2]~1066COUT1_1098 temp[3]~1067COUT1_1099 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.280 ns temp\[4\]~1068COUT1_1100 5 COMB LAB_X34_Y16 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.280 ns; Loc. = LAB_X34_Y16; Fanout = 2; COMB Node = 'temp\[4\]~1068COUT1_1100'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { temp[3]~1067COUT1_1099 temp[4]~1068COUT1_1100 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.538 ns temp\[5\]~1069 6 COMB LAB_X34_Y16 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.538 ns; Loc. = LAB_X34_Y16; Fanout = 6; COMB Node = 'temp\[5\]~1069'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { temp[4]~1068COUT1_1100 temp[5]~1069 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.674 ns temp\[10\]~1074 7 COMB LAB_X34_Y15 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.674 ns; Loc. = LAB_X34_Y15; Fanout = 6; COMB Node = 'temp\[10\]~1074'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[5]~1069 temp[10]~1074 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.810 ns temp\[15\]~1079 8 COMB LAB_X34_Y15 6 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 1.810 ns; Loc. = LAB_X34_Y15; Fanout = 6; COMB Node = 'temp\[15\]~1079'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[10]~1074 temp[15]~1079 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.946 ns temp\[20\]~1084 9 COMB LAB_X34_Y14 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 1.946 ns; Loc. = LAB_X34_Y14; Fanout = 6; COMB Node = 'temp\[20\]~1084'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[15]~1079 temp[20]~1084 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.082 ns temp\[25\]~1089 10 COMB LAB_X34_Y14 6 " "Info: 10: + IC(0.000 ns) + CELL(0.136 ns) = 2.082 ns; Loc. = LAB_X34_Y14; Fanout = 6; COMB Node = 'temp\[25\]~1089'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[20]~1084 temp[25]~1089 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.218 ns temp\[30\]~1094 11 COMB LAB_X34_Y13 1 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.218 ns; Loc. = LAB_X34_Y13; Fanout = 1; COMB Node = 'temp\[30\]~1094'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { temp[25]~1089 temp[30]~1094 } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 3.116 ns temp\[31\] 12 REG LAB_X34_Y13 2 " "Info: 12: + IC(0.000 ns) + CELL(0.898 ns) = 3.116 ns; Loc. = LAB_X34_Y13; Fanout = 2; REG Node = 'temp\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.898 ns" { temp[30]~1094 temp[31] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.508 ns ( 80.49 % ) " "Info: Total cell delay = 2.508 ns ( 80.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.608 ns ( 19.51 % ) " "Info: Total inte