dds.tan.qmsg

利用EDA硬件描述语言来实现DDS功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register reg1:u1\|q\[16\] register adder32:u2\|b\[31\] 245.22 MHz 4.078 ns Internal " "Info: Clock \"clk\" has Internal fmax of 245.22 MHz between source register \"reg1:u1\|q\[16\]\" and destination register \"adder32:u2\|b\[31\]\" (period= 4.078 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.784 ns + Longest register register " "Info: + Longest register to register delay is 3.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg1:u1\|q\[16\] 1 REG LC_X19_Y10_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y10_N2; Fanout = 3; REG Node = 'reg1:u1\|q\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reg1:u1|q[16] } "NODE_NAME" } } { "reg1.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.564 ns) 2.189 ns adder32:u2\|b\[16\]~176 2 COMB LC_X21_Y8_N0 2 " "Info: 2: + IC(1.625 ns) + CELL(0.564 ns) = 2.189 ns; Loc. = LC_X21_Y8_N0; Fanout = 2; COMB Node = 'adder32:u2\|b\[16\]~176'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.189 ns" { reg1:u1|q[16] adder32:u2|b[16]~176 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.267 ns adder32:u2\|b\[17\]~177 3 COMB LC_X21_Y8_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 2.267 ns; Loc. = LC_X21_Y8_N1; Fanout = 2; COMB Node = 'adder32:u2\|b\[17\]~177'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { adder32:u2|b[16]~176 adder32:u2|b[17]~177 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.345 ns adder32:u2\|b\[18\]~178 4 COMB LC_X21_Y8_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 2.345 ns; Loc. = LC_X21_Y8_N2; Fanout = 2; COMB Node = 'adder32:u2\|b\[18\]~178'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { adder32:u2|b[17]~177 adder32:u2|b[18]~178 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 2.423 ns adder32:u2\|b\[19\]~179 5 COMB LC_X21_Y8_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 2.423 ns; Loc. = LC_X21_Y8_N3; Fanout = 2; COMB Node = 'adder32:u2\|b\[19\]~179'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { adder32:u2|b[18]~178 adder32:u2|b[19]~179 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.601 ns adder32:u2\|b\[20\]~180 6 COMB LC_X21_Y8_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 2.601 ns; Loc. = LC_X21_Y8_N4; Fanout = 6; COMB Node = 'adder32:u2\|b\[20\]~180'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { adder32:u2|b[19]~179 adder32:u2|b[20]~180 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.809 ns adder32:u2\|b\[25\]~185 7 COMB LC_X21_Y8_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 2.809 ns; Loc. = LC_X21_Y8_N9; Fanout = 6; COMB Node = 'adder32:u2\|b\[25\]~185'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { adder32:u2|b[20]~180 adder32:u2|b[25]~185 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.945 ns adder32:u2\|b\[30\]~190 8 COMB LC_X21_Y7_N4 1 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 2.945 ns; Loc. = LC_X21_Y7_N4; Fanout = 1; COMB Node = 'adder32:u2\|b\[30\]~190'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { adder32:u2|b[25]~185 adder32:u2|b[30]~190 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.784 ns adder32:u2\|b\[31\] 9 REG LC_X21_Y7_N5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 3.784 ns; Loc. = LC_X21_Y7_N5; Fanout = 1; REG Node = 'adder32:u2\|b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.159 ns ( 57.06 % ) " "Info: Total cell delay = 2.159 ns ( 57.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.625 ns ( 42.94 % ) " "Info: Total interconnect delay = 1.625 ns ( 42.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.784 ns" { reg1:u1|q[16] adder32:u2|b[16]~176 adder32:u2|b[17]~177 adder32:u2|b[18]~178 adder32:u2|b[19]~179 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.784 ns" { reg1:u1|q[16] adder32:u2|b[16]~176 adder32:u2|b[17]~177 adder32:u2|b[18]~178 adder32:u2|b[19]~179 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } { 0.000ns 1.625ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.033 ns - Smallest " "Info: - Smallest clock skew is -0.033 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 128; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns adder32:u2\|b\[31\] 2 REG LC_X21_Y7_N5 1 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X21_Y7_N5; Fanout = 1; REG Node = 'adder32:u2\|b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 adder32:u2|b[31] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.942 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 128; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns reg1:u1\|q\[16\] 2 REG LC_X19_Y10_N2 3 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X19_Y10_N2; Fanout = 3; REG Node = 'reg1:u1\|q\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.473 ns" { clk reg1:u1|q[16] } "NODE_NAME" } } { "reg1.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk reg1:u1|q[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 reg1:u1|q[16] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 adder32:u2|b[31] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk reg1:u1|q[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 reg1:u1|q[16] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "reg1.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg1.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.784 ns" { reg1:u1|q[16] adder32:u2|b[16]~176 adder32:u2|b[17]~177 adder32:u2|b[18]~178 adder32:u2|b[19]~179 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.784 ns" { reg1:u1|q[16] adder32:u2|b[16]~176 adder32:u2|b[17]~177 adder32:u2|b[18]~178 adder32:u2|b[19]~179 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } { 0.000ns 1.625ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 adder32:u2|b[31] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.942 ns" { clk reg1:u1|q[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.942 ns" { clk clk~out0 reg1:u1|q[16] } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "adder32:u2\|b\[31\] n\[4\] clk 8.425 ns register " "Info: tsu for register \"adder32:u2\|b\[31\]\" (data pin = \"n\[4\]\", clock pin = \"clk\") is 8.425 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.297 ns + Longest pin register " "Info: + Longest pin to register delay is 11.297 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns n\[4\] 1 PIN PIN_118 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_118; Fanout = 3; PIN Node = 'n\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { n[4] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.324 ns) + CELL(0.564 ns) 9.363 ns adder32:u2\|b\[4\]~164 2 COMB LC_X21_Y10_N8 2 " "Info: 2: + IC(7.324 ns) + CELL(0.564 ns) = 9.363 ns; Loc. = LC_X21_Y10_N8; Fanout = 2; COMB Node = 'adder32:u2\|b\[4\]~164'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.888 ns" { n[4] adder32:u2|b[4]~164 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.271 ns) 9.634 ns adder32:u2\|b\[5\]~165 3 COMB LC_X21_Y10_N9 6 " "Info: 3: + IC(0.000 ns) + CELL(0.271 ns) = 9.634 ns; Loc. = LC_X21_Y10_N9; Fanout = 6; COMB Node = 'adder32:u2\|b\[5\]~165'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.271 ns" { adder32:u2|b[4]~164 adder32:u2|b[5]~165 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 9.770 ns adder32:u2\|b\[10\]~170 4 COMB LC_X21_Y9_N4 6 " "Info: 4: + IC(0.000 ns) + CELL(0.136 ns) = 9.770 ns; Loc. = LC_X21_Y9_N4; Fanout = 6; COMB Node = 'adder32:u2\|b\[10\]~170'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { adder32:u2|b[5]~165 adder32:u2|b[10]~170 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 9.978 ns adder32:u2\|b\[15\]~175 5 COMB LC_X21_Y9_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.208 ns) = 9.978 ns; Loc. = LC_X21_Y9_N9; Fanout = 6; COMB Node = 'adder32:u2\|b\[15\]~175'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { adder32:u2|b[10]~170 adder32:u2|b[15]~175 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.114 ns adder32:u2\|b\[20\]~180 6 COMB LC_X21_Y8_N4 6 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 10.114 ns; Loc. = LC_X21_Y8_N4; Fanout = 6; COMB Node = 'adder32:u2\|b\[20\]~180'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { adder32:u2|b[15]~175 adder32:u2|b[20]~180 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 10.322 ns adder32:u2\|b\[25\]~185 7 COMB LC_X21_Y8_N9 6 " "Info: 7: + IC(0.000 ns) + CELL(0.208 ns) = 10.322 ns; Loc. = LC_X21_Y8_N9; Fanout = 6; COMB Node = 'adder32:u2\|b\[25\]~185'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { adder32:u2|b[20]~180 adder32:u2|b[25]~185 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 10.458 ns adder32:u2\|b\[30\]~190 8 COMB LC_X21_Y7_N4 1 " "Info: 8: + IC(0.000 ns) + CELL(0.136 ns) = 10.458 ns; Loc. = LC_X21_Y7_N4; Fanout = 1; COMB Node = 'adder32:u2\|b\[30\]~190'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { adder32:u2|b[25]~185 adder32:u2|b[30]~190 } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 11.297 ns adder32:u2\|b\[31\] 9 REG LC_X21_Y7_N5 1 " "Info: 9: + IC(0.000 ns) + CELL(0.839 ns) = 11.297 ns; Loc. = LC_X21_Y7_N5; Fanout = 1; REG Node = 'adder32:u2\|b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.973 ns ( 35.17 % ) " "Info: Total cell delay = 3.973 ns ( 35.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.324 ns ( 64.83 % ) " "Info: Total interconnect delay = 7.324 ns ( 64.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.297 ns" { n[4] adder32:u2|b[4]~164 adder32:u2|b[5]~165 adder32:u2|b[10]~170 adder32:u2|b[15]~175 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.297 ns" { n[4] n[4]~out0 adder32:u2|b[4]~164 adder32:u2|b[5]~165 adder32:u2|b[10]~170 adder32:u2|b[15]~175 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } { 0.000ns 0.000ns 7.324ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.564ns 0.271ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 128; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns adder32:u2\|b\[31\] 2 REG LC_X21_Y7_N5 1 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X21_Y7_N5; Fanout = 1; REG Node = 'adder32:u2\|b\[31\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "adder32.vhd" "" { Text "F:/EDA技术与VHDL/dds/adder32.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 adder32:u2|b[31] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.297 ns" { n[4] adder32:u2|b[4]~164 adder32:u2|b[5]~165 adder32:u2|b[10]~170 adder32:u2|b[15]~175 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.297 ns" { n[4] n[4]~out0 adder32:u2|b[4]~164 adder32:u2|b[5]~165 adder32:u2|b[10]~170 adder32:u2|b[15]~175 adder32:u2|b[20]~180 adder32:u2|b[25]~185 adder32:u2|b[30]~190 adder32:u2|b[31] } { 0.000ns 0.000ns 7.324ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.475ns 0.564ns 0.271ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk adder32:u2|b[31] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 adder32:u2|b[31] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk p\[29\] reg2:u3\|p\[29\] 8.211 ns register " "Info: tco from clock \"clk\" to destination pin \"p\[29\]\" through register \"reg2:u3\|p\[29\]\" is 8.211 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 128; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns reg2:u3\|p\[29\] 2 REG LC_X12_Y10_N2 1 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'reg2:u3\|p\[29\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.456 ns" { clk reg2:u3|p[29] } "NODE_NAME" } } { "reg2.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.53 % ) " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk reg2:u3|p[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 reg2:u3|p[29] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "reg2.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg2.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.062 ns + Longest register pin " "Info: + Longest register to pin delay is 5.062 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg2:u3\|p\[29\] 1 REG LC_X12_Y10_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y10_N2; Fanout = 1; REG Node = 'reg2:u3\|p\[29\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reg2:u3|p[29] } "NODE_NAME" } } { "reg2.vhd" "" { Text "F:/EDA技术与VHDL/dds/reg2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.938 ns) + CELL(2.124 ns) 5.062 ns p\[29\] 2 PIN PIN_19 0 " "Info: 2: + IC(2.938 ns) + CELL(2.124 ns) = 5.062 ns; Loc. = PIN_19; Fanout = 0; PIN Node = 'p\[29\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.062 ns" { reg2:u3|p[29] p[29] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 41.96 % ) " "Info: Total cell delay = 2.124 ns ( 41.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.938 ns ( 58.04 % ) " "Info: Total interconnect delay = 2.938 ns ( 58.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.062 ns" { reg2:u3|p[29] p[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.062 ns" { reg2:u3|p[29] p[29] } { 0.000ns 2.938ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.925 ns" { clk reg2:u3|p[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 reg2:u3|p[29] } { 0.000ns 0.000ns 0.745ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.062 ns" { reg2:u3|p[29] p[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.062 ns" { reg2:u3|p[29] p[29] } { 0.000ns 2.938ns } { 0.000ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "sum32:u0\|temp\[22\] k\[22\] clk -4.631 ns register " "Info: th for register \"sum32:u0\|temp\[22\]\" (data pin = \"k\[22\]\", clock pin = \"clk\") is -4.631 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.909 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 128 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 128; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.729 ns) + CELL(0.711 ns) 2.909 ns sum32:u0\|temp\[22\] 2 REG LC_X24_Y8_N6 4 " "Info: 2: + IC(0.729 ns) + CELL(0.711 ns) = 2.909 ns; Loc. = LC_X24_Y8_N6; Fanout = 4; REG Node = 'sum32:u0\|temp\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.440 ns" { clk sum32:u0|temp[22] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.94 % ) " "Info: Total cell delay = 2.180 ns ( 74.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.729 ns ( 25.06 % ) " "Info: Total interconnect delay = 0.729 ns ( 25.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk sum32:u0|temp[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 sum32:u0|temp[22] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.555 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns k\[22\] 1 PIN PIN_99 3 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_99; Fanout = 3; PIN Node = 'k\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { k[22] } "NODE_NAME" } } { "dds.vhd" "" { Text "F:/EDA技术与VHDL/dds/dds.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.473 ns) + CELL(0.607 ns) 7.555 ns sum32:u0\|temp\[22\] 2 REG LC_X24_Y8_N6 4 " "Info: 2: + IC(5.473 ns) + CELL(0.607 ns) = 7.555 ns; Loc. = LC_X24_Y8_N6; Fanout = 4; REG Node = 'sum32:u0\|temp\[22\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.080 ns" { k[22] sum32:u0|temp[22] } "NODE_NAME" } } { "sum32.vhd" "" { Text "F:/EDA技术与VHDL/dds/sum32.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.082 ns ( 27.56 % ) " "Info: Total cell delay = 2.082 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.473 ns ( 72.44 % ) " "Info: Total interconnect delay = 5.473 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.555 ns" { k[22] sum32:u0|temp[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.555 ns" { k[22] k[22]~out0 sum32:u0|temp[22] } { 0.000ns 0.000ns 5.473ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.909 ns" { clk sum32:u0|temp[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.909 ns" { clk clk~out0 sum32:u0|temp[22] } { 0.000ns 0.000ns 0.729ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.555 ns" { k[22] sum32:u0|temp[22] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.555 ns" { k[22] k[22]~out0 sum32:u0|temp[22] } { 0.000ns 0.000ns 5.473ns } { 0.000ns 1.475ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}