📄 gmajcounter.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\eda experiment\count 999\gmajcounter.rpt
gmajcounter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 10/ 96( 10%) 0/ 48( 0%) 4/ 48( 8%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\eda experiment\count 999\gmajcounter.rpt
gmajcounter
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
ch0 : INPUT;
ch1 : INPUT;
ch2 : INPUT;
c0 : INPUT;
c1 : INPUT;
c2 : INPUT;
c3 : INPUT;
-- Node name is 'dataout0'
-- Equation name is 'dataout0', type is output
dataout0 = _LC8_B18;
-- Node name is 'dataout1'
-- Equation name is 'dataout1', type is output
dataout1 = _LC1_B18;
-- Node name is 'dataout2'
-- Equation name is 'dataout2', type is output
dataout2 = _LC7_B22;
-- Node name is 'dataout3'
-- Equation name is 'dataout3', type is output
dataout3 = _LC1_B22;
-- Node name is ':22'
-- Equation name is '_LC3_B18', type is buried
!_LC3_B18 = _LC3_B18~NOT;
_LC3_B18~NOT = LCELL( _EQ001);
_EQ001 = ch2
# ch1
# ch0;
-- Node name is ':40'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = LCELL( _EQ002);
_EQ002 = b3 & ch0 & !ch1 & !ch2;
-- Node name is ':41'
-- Equation name is '_LC3_B22', type is buried
_LC3_B22 = LCELL( _EQ003);
_EQ003 = ch2 & c3
# ch1 & c3
# !ch0 & c3;
-- Node name is ':45'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = LCELL( _EQ004);
_EQ004 = a3 & _LC3_B18
# !_LC3_B18 & _LC3_B22
# !_LC3_B18 & _LC4_B22;
-- Node name is ':52'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = LCELL( _EQ005);
_EQ005 = b2 & ch0 & !ch1 & !ch2;
-- Node name is ':53'
-- Equation name is '_LC2_B18', type is buried
_LC2_B18 = LCELL( _EQ006);
_EQ006 = ch2 & c2
# ch1 & c2
# !ch0 & c2;
-- Node name is ':54'
-- Equation name is '_LC7_B22', type is buried
_LC7_B22 = LCELL( _EQ007);
_EQ007 = a2 & _LC3_B18
# _LC2_B18 & !_LC3_B18
# _LC2_B22 & !_LC3_B18;
-- Node name is ':61'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ008);
_EQ008 = b1 & ch0 & !ch1 & !ch2;
-- Node name is ':62'
-- Equation name is '_LC6_B18', type is buried
_LC6_B18 = LCELL( _EQ009);
_EQ009 = ch2 & c1
# ch1 & c1
# !ch0 & c1;
-- Node name is ':63'
-- Equation name is '_LC1_B18', type is buried
_LC1_B18 = LCELL( _EQ010);
_EQ010 = a1 & _LC3_B18
# !_LC3_B18 & _LC6_B18
# !_LC3_B18 & _LC7_B18;
-- Node name is ':70'
-- Equation name is '_LC5_B18', type is buried
_LC5_B18 = LCELL( _EQ011);
_EQ011 = b0 & ch0 & !ch1 & !ch2;
-- Node name is ':71'
-- Equation name is '_LC4_B18', type is buried
_LC4_B18 = LCELL( _EQ012);
_EQ012 = ch2 & c0
# ch1 & c0
# !ch0 & c0;
-- Node name is ':72'
-- Equation name is '_LC8_B18', type is buried
_LC8_B18 = LCELL( _EQ013);
_EQ013 = a0 & _LC3_B18
# !_LC3_B18 & _LC4_B18
# !_LC3_B18 & _LC5_B18;
Project Information d:\eda experiment\count 999\gmajcounter.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,346K
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