📄 seg7.rpt
字号:
- 5 - B 01 OR2 4 0 1 0 :518
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\eda experiment\count 999\seg7.rpt
seg7
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\eda experiment\count 999\seg7.rpt
seg7
** EQUATIONS **
q0 : INPUT;
q1 : INPUT;
q2 : INPUT;
q3 : INPUT;
-- Node name is 'segment0'
-- Equation name is 'segment0', type is output
segment0 = _LC5_B1;
-- Node name is 'segment1'
-- Equation name is 'segment1', type is output
segment1 = _LC1_B1;
-- Node name is 'segment2'
-- Equation name is 'segment2', type is output
segment2 = _LC3_B1;
-- Node name is 'segment3'
-- Equation name is 'segment3', type is output
segment3 = _LC4_B1;
-- Node name is 'segment4'
-- Equation name is 'segment4', type is output
segment4 = _LC6_B1;
-- Node name is 'segment5'
-- Equation name is 'segment5', type is output
segment5 = _LC8_B1;
-- Node name is 'segment6'
-- Equation name is 'segment6', type is output
segment6 = _LC2_B1;
-- Node name is ':340'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ001);
_EQ001 = q3
# !q1 & q2
# q0 & q2
# q0 & q1
# q1 & !q2;
-- Node name is ':368'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = LCELL( _EQ002);
_EQ002 = q3
# q2
# !q0 & !q1;
-- Node name is ':398'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = LCELL( _EQ003);
_EQ003 = !q0 & !q2
# q1 & q3
# q2 & q3
# !q0 & q3
# q0 & q2;
-- Node name is ':428'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = LCELL( _EQ004);
_EQ004 = q3
# q1 & !q2
# !q0 & !q2
# q0 & q2
# q0 & q1;
-- Node name is ':458'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = LCELL( _EQ005);
_EQ005 = q0 & !q2 & !q3
# !q0 & q2 & !q3
# !q1 & !q3
# !q1 & !q2;
-- Node name is ':488'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = LCELL( _EQ006);
_EQ006 = !q2 & !q3
# !q0 & !q3
# !q1 & !q2;
-- Node name is ':518'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = LCELL( _EQ007);
_EQ007 = q3
# q1
# q0 & q2
# !q0 & !q2;
Project Information d:\eda experiment\count 999\seg7.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,501K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -