traffic.tan.qmsg

vhdl实现交通灯设计,可以实现十字路口处交通控制,开发工具quartus

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnum\[0\]~reg0 cnum\[0\]~reg0 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"cnum\[0\]~reg0\" and destination register \"cnum\[0\]~reg0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.168 ns + Longest register register " "Info: + Longest register to register delay is 3.168 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnum\[0\]~reg0 1 REG LC_X20_Y5_N1 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.549 ns) + CELL(0.590 ns) 1.139 ns Equal0~56 2 COMB LC_X20_Y5_N8 1 " "Info: 2: + IC(0.549 ns) + CELL(0.590 ns) = 1.139 ns; Loc. = LC_X20_Y5_N8; Fanout = 1; COMB Node = 'Equal0~56'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.139 ns" { cnum[0]~reg0 Equal0~56 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 1.435 ns Equal0~57 3 COMB LC_X20_Y5_N9 9 " "Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 1.435 ns; Loc. = LC_X20_Y5_N9; Fanout = 9; COMB Node = 'Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.296 ns" { Equal0~56 Equal0~57 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.508 ns) + CELL(1.225 ns) 3.168 ns cnum\[0\]~reg0 4 REG LC_X20_Y5_N1 5 " "Info: 4: + IC(0.508 ns) + CELL(1.225 ns) = 3.168 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { Equal0~57 cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 60.89 % ) " "Info: Total cell delay = 1.929 ns ( 60.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.239 ns ( 39.11 % ) " "Info: Total interconnect delay = 1.239 ns ( 39.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnum[0]~reg0 Equal0~56 Equal0~57 cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { cnum[0]~reg0 {} Equal0~56 {} Equal0~57 {} cnum[0]~reg0 {} } { 0.000ns 0.549ns 0.182ns 0.508ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.853 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.673 ns) + CELL(0.711 ns) 6.853 ns cnum\[0\]~reg0 2 REG LC_X20_Y5_N1 5 " "Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.81 % ) " "Info: Total cell delay = 2.180 ns ( 31.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.673 ns ( 68.19 % ) " "Info: Total interconnect delay = 4.673 ns ( 68.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.853 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.673 ns) + CELL(0.711 ns) 6.853 ns cnum\[0\]~reg0 2 REG LC_X20_Y5_N1 5 " "Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.81 % ) " "Info: Total cell delay = 2.180 ns ( 31.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.673 ns ( 68.19 % ) " "Info: Total interconnect delay = 4.673 ns ( 68.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { cnum[0]~reg0 Equal0~56 Equal0~57 cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.168 ns" { cnum[0]~reg0 {} Equal0~56 {} Equal0~57 {} cnum[0]~reg0 {} } { 0.000ns 0.549ns 0.182ns 0.508ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { cnum[0]~reg0 {} } {  } {  } "" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "current_state.s0 reset clk 1.785 ns register " "Info: tsu for register \"current_state.s0\" (data pin = \"reset\", clock pin = \"clk\") is 1.785 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.601 ns + Longest pin register " "Info: + Longest pin to register delay is 8.601 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns reset 1 PIN PIN_61 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_61; Fanout = 7; PIN Node = 'reset'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.514 ns) + CELL(0.590 ns) 7.579 ns current_state.s0~105 2 COMB LC_X21_Y5_N4 3 " "Info: 2: + IC(5.514 ns) + CELL(0.590 ns) = 7.579 ns; Loc. = LC_X21_Y5_N4; Fanout = 3; COMB Node = 'current_state.s0~105'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.104 ns" { reset current_state.s0~105 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.309 ns) 8.601 ns current_state.s0 3 REG LC_X20_Y5_N0 5 " "Info: 3: + IC(0.713 ns) + CELL(0.309 ns) = 8.601 ns; Loc. = LC_X20_Y5_N0; Fanout = 5; REG Node = 'current_state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { current_state.s0~105 current_state.s0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 27.60 % ) " "Info: Total cell delay = 2.374 ns ( 27.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.227 ns ( 72.40 % ) " "Info: Total interconnect delay = 6.227 ns ( 72.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.601 ns" { reset current_state.s0~105 current_state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.601 ns" { reset {} reset~out0 {} current_state.s0~105 {} current_state.s0 {} } { 0.000ns 0.000ns 5.514ns 0.713ns } { 0.000ns 1.475ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.853 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 6.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.673 ns) + CELL(0.711 ns) 6.853 ns current_state.s0 2 REG LC_X20_Y5_N0 5 " "Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N0; Fanout = 5; REG Node = 'current_state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { clk current_state.s0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.81 % ) " "Info: Total cell delay = 2.180 ns ( 31.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.673 ns ( 68.19 % ) " "Info: Total interconnect delay = 4.673 ns ( 68.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk current_state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} current_state.s0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.601 ns" { reset current_state.s0~105 current_state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.601 ns" { reset {} reset~out0 {} current_state.s0~105 {} current_state.s0 {} } { 0.000ns 0.000ns 5.514ns 0.713ns } { 0.000ns 1.475ns 0.590ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk current_state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} current_state.s0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk cnum\[2\] cnum\[2\]~reg0 12.060 ns register " "Info: tco from clock \"clk\" to destination pin \"cnum\[2\]\" through register \"cnum\[2\]~reg0\" is 12.060 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.853 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.673 ns) + CELL(0.711 ns) 6.853 ns cnum\[2\]~reg0 2 REG LC_X20_Y5_N3 5 " "Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N3; Fanout = 5; REG Node = 'cnum\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { clk cnum[2]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.81 % ) " "Info: Total cell delay = 2.180 ns ( 31.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.673 ns ( 68.19 % ) " "Info: Total interconnect delay = 4.673 ns ( 68.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[2]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.983 ns + Longest register pin " "Info: + Longest register to pin delay is 4.983 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnum\[2\]~reg0 1 REG LC_X20_Y5_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y5_N3; Fanout = 5; REG Node = 'cnum\[2\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnum[2]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.859 ns) + CELL(2.124 ns) 4.983 ns cnum\[2\] 2 PIN PIN_26 0 " "Info: 2: + IC(2.859 ns) + CELL(2.124 ns) = 4.983 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'cnum\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.983 ns" { cnum[2]~reg0 cnum[2] } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 42.62 % ) " "Info: Total cell delay = 2.124 ns ( 42.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.859 ns ( 57.38 % ) " "Info: Total interconnect delay = 2.859 ns ( 57.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.983 ns" { cnum[2]~reg0 cnum[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.983 ns" { cnum[2]~reg0 {} cnum[2] {} } { 0.000ns 2.859ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[2]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[2]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.983 ns" { cnum[2]~reg0 cnum[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.983 ns" { cnum[2]~reg0 {} cnum[2] {} } { 0.000ns 2.859ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "cnum\[0\]~reg0 hold clk -1.015 ns register " "Info: th for register \"cnum\[0\]~reg0\" (data pin = \"hold\", clock pin = \"clk\") is -1.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.853 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_27 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_27; Fanout = 9; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.673 ns) + CELL(0.711 ns) 6.853 ns cnum\[0\]~reg0 2 REG LC_X20_Y5_N1 5 " "Info: 2: + IC(4.673 ns) + CELL(0.711 ns) = 6.853 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.384 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.81 % ) " "Info: Total cell delay = 2.180 ns ( 31.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.673 ns ( 68.19 % ) " "Info: Total interconnect delay = 4.673 ns ( 68.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.883 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns hold 1 PIN PIN_60 7 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_60; Fanout = 7; PIN Node = 'hold'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hold } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.541 ns) + CELL(0.867 ns) 7.883 ns cnum\[0\]~reg0 2 REG LC_X20_Y5_N1 5 " "Info: 2: + IC(5.541 ns) + CELL(0.867 ns) = 7.883 ns; Loc. = LC_X20_Y5_N1; Fanout = 5; REG Node = 'cnum\[0\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.408 ns" { hold cnum[0]~reg0 } "NODE_NAME" } } { "counter1.vhd" "" { Text "F:/vhdl traffic light/traffic/counter1.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 29.71 % ) " "Info: Total cell delay = 2.342 ns ( 29.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.541 ns ( 70.29 % ) " "Info: Total interconnect delay = 5.541 ns ( 70.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { hold cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { hold {} hold~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.853 ns" { clk {} clk~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 4.673ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { hold cnum[0]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { hold {} hold~out0 {} cnum[0]~reg0 {} } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}