abs_divider_cag.tdf

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--abs_divider DEN_REPRESENTATION="SIGNED" LPM_PIPELINE=0 MAXIMIZE_SPEED=9 NUM_REPRESENTATION="SIGNED" SKIP_BITS=0 WIDTH_D=5 WIDTH_N=9 denominator numerator quotient remainder
--VERSION_BEGIN 7.2 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_lpm_divide 2007:01:30:03:58:02:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:05:02:16:27:14:SJ cbx_stratixii 2007:06:28:17:26:26:SJ cbx_util_mgl 2007:06:01:06:37:30:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION alt_u_div_eoe (denominator[4..0], numerator[8..0])
RETURNS ( den_out[4..0], quotient[8..0], remainder[4..0]);
FUNCTION lpm_abs_ui9 (data[4..0])
RETURNS ( result[4..0]);
FUNCTION lpm_abs_2j9 (data[8..0])
RETURNS ( overflow, result[8..0]);
FUNCTION add_sub_25f (cin, dataa[8..0], datab[8..0])
RETURNS ( result[8..0]);
FUNCTION add_sub_u4f (cin, dataa[4..0], datab[4..0])
RETURNS ( result[4..0]);

--synthesis_resources = lut 19 
SUBDESIGN abs_divider_cag
( 
	denominator[4..0]	:	input;
	numerator[8..0]	:	input;
	quotient[8..0]	:	output;
	remainder[4..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_eoe;
	my_abs_den : lpm_abs_ui9;
	my_abs_num : lpm_abs_2j9;
	compl_add_quot : add_sub_25f;
	compl_add_rem : add_sub_u4f;
	diff_signs	: WIRE;
	gnd_wire	: WIRE;
	neg_quot[8..0]	: WIRE;
	neg_rem[4..0]	: WIRE;
	norm_den[4..0]	: WIRE;
	norm_num[8..0]	: WIRE;
	num_sign	: WIRE;
	protect_quotient[8..0]	: WIRE;
	protect_remainder[4..0]	: WIRE;
	vcc_wire	: WIRE;

BEGIN 
	divider.denominator[] = norm_den[];
	divider.numerator[] = norm_num[];
	my_abs_den.data[] = denominator[];
	my_abs_num.data[] = numerator[];
	compl_add_quot.cin = vcc_wire;
	compl_add_quot.dataa[] = (! protect_quotient[]);
	compl_add_quot.datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
	compl_add_rem.cin = vcc_wire;
	compl_add_rem.dataa[] = (! protect_remainder[]);
	compl_add_rem.datab[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire, gnd_wire);
	diff_signs = (numerator[8..8] $ denominator[4..4]);
	gnd_wire = B"0";
	neg_quot[] = compl_add_quot.result[];
	neg_rem[] = compl_add_rem.result[];
	norm_den[] = my_abs_den.result[];
	norm_num[] = my_abs_num.result[];
	num_sign = numerator[8..8];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = ((protect_quotient[] & (! diff_signs)) # (neg_quot[] & diff_signs));
	remainder[] = ((protect_remainder[] & (! num_sign)) # (neg_rem[] & num_sign));
	vcc_wire = B"1";
END;
--VALID FILE