dec_3x8.v

来自「8對3編碼器 解多工器 用於整合 可輕易改成16對4」· Verilog 代码 · 共 24 行

module DEC_3X8(i0, i1, i2, enable, out);
input i0, i1, i2, enable;
output [7:0]out;
reg [7:0]out;
always @(enable or i0 or i1 or i2)
begin
      if (enable == 1'b1)
begin
      case ({i0, i1, i2})
            3'b000: out = 8'b00000001;
            3'b001: out = 8'b00000010;
            3'b010: out = 8'b00000100;
            3'b011: out = 8'b00001000;
            3'b100: out = 8'b00010000;
            3'b101: out = 8'b00100000;
            3'b110: out = 8'b01000000;
            3'b111: out = 8'b10000000;             
      endcase
      end
else
      out = 8'b00000000;
end
endmodule