sdram_top.vhd

sdram controller 2 vhdl

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--
-- Title       : No Title
-- Design      : SDR_controller
-- Author      : Michal Krepa
-- Company     : XXX
--
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--
-- File        : c:\My_Designs\SDR_controller\SDR_controller\compile\sdram_top.vhd
-- Generated   : Sun Oct 26 17:17:49 2003
-- From        : c:\My_Designs\SDR_controller\SDR_controller\src\sdram_top.bde
-- By          : Bde2Vhdl ver. 2.5
--
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--
-- Description : 
--
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-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;


entity sdram_top is
  port(
       CLK : in STD_LOGIC;
       WnR : in STD_LOGIC;
       nAS : in STD_LOGIC;
       nRST : in STD_LOGIC;
       ADDR : in STD_LOGIC_VECTOR(20 downto 0);
       DIN : in STD_LOGIC_VECTOR(31 downto 0);
       nLBE : in STD_LOGIC_VECTOR(3 downto 0);
       nDTACK : out STD_LOGIC;
       DOUT : out STD_LOGIC_VECTOR(31 downto 0)
  );
end sdram_top;

architecture sdram_top of sdram_top is

---- Component declarations -----

component SDRAM_32
  port (
       A : in STD_LOGIC_VECTOR(10 downto 0);
       BS : in STD_LOGIC_VECTOR(1 downto 0);
       CKE : in STD_LOGIC;
       CLK : in STD_LOGIC;
       DQM : in STD_LOGIC_VECTOR(3 downto 0);
       DQ_IN : in STD_LOGIC_VECTOR(31 downto 0);
       nCAS : in STD_LOGIC;
       nCS : in STD_LOGIC;
       nRAS : in STD_LOGIC;
       nWE : in STD_LOGIC;
       DQ_DiR : out STD_LOGIC_VECTOR(3 downto 0);
       DQ_OUT : out STD_LOGIC_VECTOR(31 downto 0)
  );
end component;
component SDR_CTRL
  generic(
       columns : POSITIVE := 256;
       data_width : POSITIVE := 32;
       haddr_width : POSITIVE := 21;
       rows : POSITIVE := 2048;
       saddr_width : POSITIVE := 11
  );
  port (
       ADDR : in STD_LOGIC_VECTOR(haddr_width-1 downto 0);
       CLK : in STD_LOGIC;
       DATA_IN : in STD_LOGIC_VECTOR(data_width-1 downto 0);
       WnR : in STD_LOGIC;
       nAS : in STD_LOGIC;
       nLBE : in STD_LOGIC_VECTOR(data_width/8-1 downto 0);
       nRST : in STD_LOGIC;
       A : out STD_LOGIC_VECTOR(saddr_width-1 downto 0);
       BS : out STD_LOGIC_VECTOR(1 downto 0);
       CKE : out STD_LOGIC;
       DATA_OUT_SDR : out STD_LOGIC_VECTOR(data_width-1 downto 0);
       DQM : out STD_LOGIC_VECTOR(data_width/8-1 downto 0);
       nCAS : out STD_LOGIC;
       nCS : out STD_LOGIC;
       nDTACK : out STD_LOGIC;
       nRAS : out STD_LOGIC;
       nWE : out STD_LOGIC
  );
end component;

---- Signal declarations used on the diagram ----

signal CKE_SDR : STD_LOGIC;
signal nCAS_SDR : STD_LOGIC;
signal nCS_SDR : STD_LOGIC;
signal nRAS_SDR : STD_LOGIC;
signal nWE_SDR : STD_LOGIC;
signal A_SDR : STD_LOGIC_VECTOR (10 downto 0);
signal BS_SDR : STD_LOGIC_VECTOR (1 downto 0);
signal DIN_SDR : STD_LOGIC_VECTOR (31 downto 0);
signal DQM_SDR : STD_LOGIC_VECTOR (3 downto 0);

begin

----  Component instantiations  ----

U1 : SDRAM_32
  port map(
       A => A_SDR,
       BS => BS_SDR,
       CKE => CKE_SDR,
       CLK => CLK,
       DQM => DQM_SDR,
       DQ_IN => DIN_SDR,
       DQ_OUT => DOUT,
       nCAS => nCAS_SDR,
       nCS => nCS_SDR,
       nRAS => nRAS_SDR,
       nWE => nWE_SDR
  );

U2 : SDR_CTRL
  generic map (
       columns => 256,
       data_width => 32,
       haddr_width => 21,
       rows => 2048,
       saddr_width => 11
  )
  port map(
       A => A_SDR( 10 downto 0 ),
       ADDR => ADDR( 20 downto 0 ),
       BS => BS_SDR,
       CKE => CKE_SDR,
       CLK => CLK,
       DATA_IN => DIN( 31 downto 0 ),
       DATA_OUT_SDR => DIN_SDR( 31 downto 0 ),
       DQM => DQM_SDR( 3 downto 0 ),
       WnR => WnR,
       nAS => nAS,
       nCAS => nCAS_SDR,
       nCS => nCS_SDR,
       nDTACK => nDTACK,
       nLBE => nLBE( 3 downto 0 ),
       nRAS => nRAS_SDR,
       nRST => nRST,
       nWE => nWE_SDR
  );


end sdram_top;