xiaodou2.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xiaodou2 is
port  (		gclk	 	      	:  in std_logic;  
       		shuru       		:  in std_logic; 
		 	rst        			:  in std_logic;
       		rxout    	   		:  out std_logic);	    
end xiaodou2;

architecture Behavioral of xiaodou2 is
	signal     		count          : std_logic_vector(2 downto 0); 
	signal    	 	dout           : std_logic; 
	
begin

process (gclk,rst)
	begin
		if rst = '1' then
			rxout <= '0';
			dout <= '0';
			count <= "000";
		elsif gclk ' event and gclk = '1' then
			if (shuru = '0') and (count(2) = '0') and (dout = '1') then
				dout <= '1';
				count <= count+1;
			elsif (shuru = '0') and (count(2) = '1') and (dout = '1') then
				dout <= '0';
				count <= "000";
			elsif (shuru = '1') and (count(2) = '0') and (dout = '0') then
				dout <= '0';
				count <= count+1;
			elsif (shuru = '1') and (count(2) = '1') and (dout = '0') then
				dout <= '1';
				count <= "000";
			else
				rxout <= dout;
				count <= "000";
			end if;
		end if;
	end process;

end Behavioral;