mlt.map.rpt

VHDL 乘法器 源代码

;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 7     ;
;     -- 3 input functions                    ; 0     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 0     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 7     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 0     ;
; I/O pins                                    ; 20    ;
; Maximum fan-out node                        ; b[1]  ;
; Maximum fan-out                             ; 7     ;
; Total fan-out                               ; 35    ;
; Average fan-out                             ; 1.30  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |mlt                       ; 7 (7)       ; 0            ; 0           ; 0            ; 0       ; 0         ; 0         ; 20   ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |mlt                ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_mult:Mult0                 ;
+------------------------------------------------+----------+---------------------+
; Parameter Name                                 ; Value    ; Type                ;
+------------------------------------------------+----------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON       ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF      ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON       ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF      ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 2        ; Untyped             ;
; LPM_WIDTHB                                     ; 2        ; Untyped             ;
; LPM_WIDTHP                                     ; 4        ; Untyped             ;
; LPM_WIDTHR                                     ; 4        ; Untyped             ;
; LPM_WIDTHS                                     ; 1        ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED ; Untyped             ;
; LPM_PIPELINE                                   ; 0        ; Untyped             ;
; LATENCY                                        ; 0        ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO       ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO       ; Untyped             ;
; USE_EAB                                        ; OFF      ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5        ; Untyped             ;
; DEVICE_FAMILY                                  ; MAX II   ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL   ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT      ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO     ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0        ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0        ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx       ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx       ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF      ; Untyped             ;
+------------------------------------------------+----------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance         ;
+---------------------------------------+----------------+
; Name                                  ; Value          ;
+---------------------------------------+----------------+
; Number of entity instances            ; 1              ;
; Entity Instance                       ; lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 2              ;
;     -- LPM_WIDTHB                     ; 2              ;
;     -- LPM_WIDTHP                     ; 4              ;
;     -- LPM_REPRESENTATION             ; UNSIGNED       ;
;     -- INPUT_A_IS_CONSTANT            ; NO             ;
;     -- INPUT_B_IS_CONSTANT            ; NO             ;
;     -- USE_EAB                        ; OFF            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx             ;
+---------------------------------------+----------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Fri Apr 17 17:34:16 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mlt -c mlt
Info: Found 2 design units, including 1 entities, in source file mlt.vhd
    Info: Found design unit 1: mlt-arch
    Info: Found entity 1: mlt
Info: Elaborating entity "mlt" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "Mult0"
Info: Elaborated megafunction instantiation "lpm_mult:Mult0"
Info: Instantiated megafunction "lpm_mult:Mult0" with the following parameter:
    Info: Parameter "LPM_WIDTHA" = "2"
    Info: Parameter "LPM_WIDTHB" = "2"
    Info: Parameter "LPM_WIDTHP" = "4"
    Info: Parameter "LPM_WIDTHR" = "4"
    Info: Parameter "LPM_WIDTHS" = "1"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info: Parameter "MAXIMIZE_SPEED" = "5"
    Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"
Info: Elaborated megafunction instantiation "lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "lpm_mult:Mult0"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "c[0]" is stuck at VCC
    Warning (13410): Pin "en[0]" is stuck at GND
    Warning (13410): Pin "en[1]" is stuck at VCC
    Warning (13410): Pin "en[2]" is stuck at VCC
    Warning (13410): Pin "en[3]" is stuck at VCC
    Warning (13410): Pin "en[4]" is stuck at VCC
    Warning (13410): Pin "en[5]" is stuck at VCC
    Warning (13410): Pin "en[6]" is stuck at VCC
    Warning (13410): Pin "en[7]" is stuck at VCC
Info: Implemented 27 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Peak virtual memory: 174 megabytes
    Info: Processing ended: Fri Apr 17 17:34:20 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:03