paddr.map.qmsg

4位二进制加法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 06 16:42:52 2009 " "Info: Processing started: Mon Apr 06 16:42:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off paddr -c paddr " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off paddr -c paddr" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "paddr.vhd 6 3 " "Info: Found 6 design units, including 3 entities, in source file paddr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 paddr-be " "Info: Found design unit 1: paddr-be" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 seg7-behave " "Info: Found design unit 2: seg7-behave" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 padder-be " "Info: Found design unit 3: padder-be" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 109 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 paddr " "Info: Found entity 1: paddr" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 seg7 " "Info: Found entity 2: seg7" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 padder " "Info: Found entity 3: padder" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 96 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "padder " "Info: Elaborating entity \"padder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "paddr paddr:u1 " "Info: Elaborating entity \"paddr\" for hierarchy \"paddr:u1\"" {  } { { "paddr.vhd" "u1" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 126 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "C4 paddr.vhd(15) " "Warning (10036): Verilog HDL or VHDL warning at paddr.vhd(15): object \"C4\" assigned a value but never read" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 15 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seg7 seg7:u2 " "Info: Elaborating entity \"seg7\" for hierarchy \"seg7:u2\"" {  } { { "paddr.vhd" "u2" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 130 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg1\[7\] VCC " "Warning (13410): Pin \"seg1\[7\]\" is stuck at VCC" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 103 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg2\[7\] VCC " "Warning (13410): Pin \"seg2\[7\]\" is stuck at VCC" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 104 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "seg3\[7\] VCC " "Warning (13410): Pin \"seg3\[7\]\" is stuck at VCC" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 105 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "E " "Warning (15610): No output dependent on input pin \"E\"" {  } { { "paddr.vhd" "" { Text "C:/Users/zhang/Desktop/lab2-1/lab2-2/paddr.vhd" 102 -1 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "65 " "Info: Implemented 65 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "24 " "Info: Implemented 24 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "31 " "Info: Implemented 31 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "213 " "Info: Peak virtual memory: 213 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 06 16:42:54 2009 " "Info: Processing ended: Mon Apr 06 16:42:54 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}