paddr.tan.rpt

4位二进制加法器

Classic Timing Analyzer report for paddr
Mon Apr 06 16:43:24 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                    ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 16.825 ns   ; C0   ; seg3[0] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+---------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C70F896C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------+
; tpd                                                          ;
+-------+-------------------+-----------------+------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To      ;
+-------+-------------------+-----------------+------+---------+
; N/A   ; None              ; 16.825 ns       ; C0   ; seg3[0] ;
; N/A   ; None              ; 16.534 ns       ; C0   ; seg3[2] ;
; N/A   ; None              ; 16.001 ns       ; Y2   ; seg3[0] ;
; N/A   ; None              ; 15.926 ns       ; X2   ; seg3[0] ;
; N/A   ; None              ; 15.871 ns       ; Y1   ; seg3[0] ;
; N/A   ; None              ; 15.739 ns       ; C0   ; seg3[3] ;
; N/A   ; None              ; 15.715 ns       ; Y2   ; seg3[2] ;
; N/A   ; None              ; 15.660 ns       ; X1   ; seg3[0] ;
; N/A   ; None              ; 15.640 ns       ; X2   ; seg3[2] ;
; N/A   ; None              ; 15.582 ns       ; C0   ; seg3[1] ;
; N/A   ; None              ; 15.580 ns       ; Y1   ; seg3[2] ;
; N/A   ; None              ; 15.571 ns       ; Y3   ; seg3[0] ;
; N/A   ; None              ; 15.560 ns       ; X3   ; seg3[0] ;
; N/A   ; None              ; 15.369 ns       ; X1   ; seg3[2] ;
; N/A   ; None              ; 15.280 ns       ; Y3   ; seg3[2] ;
; N/A   ; None              ; 15.269 ns       ; X3   ; seg3[2] ;
; N/A   ; None              ; 14.947 ns       ; Y2   ; seg3[3] ;
; N/A   ; None              ; 14.929 ns       ; C0   ; seg3[5] ;
; N/A   ; None              ; 14.889 ns       ; C0   ; seg3[6] ;
; N/A   ; None              ; 14.872 ns       ; X2   ; seg3[3] ;
; N/A   ; None              ; 14.785 ns       ; Y1   ; seg3[3] ;
; N/A   ; None              ; 14.763 ns       ; Y2   ; seg3[1] ;
; N/A   ; None              ; 14.690 ns       ; Y4   ; seg3[0] ;
; N/A   ; None              ; 14.688 ns       ; X2   ; seg3[1] ;
; N/A   ; None              ; 14.628 ns       ; Y1   ; seg3[1] ;
; N/A   ; None              ; 14.619 ns       ; C0   ; seg3[4] ;
; N/A   ; None              ; 14.574 ns       ; X1   ; seg3[3] ;
; N/A   ; None              ; 14.553 ns       ; X4   ; seg3[0] ;
; N/A   ; None              ; 14.485 ns       ; Y3   ; seg3[3] ;
; N/A   ; None              ; 14.474 ns       ; X3   ; seg3[3] ;
; N/A   ; None              ; 14.417 ns       ; X1   ; seg3[1] ;
; N/A   ; None              ; 14.399 ns       ; Y4   ; seg3[2] ;
; N/A   ; None              ; 14.328 ns       ; Y3   ; seg3[1] ;
; N/A   ; None              ; 14.317 ns       ; X3   ; seg3[1] ;