paddr.vhd

4位二进制加法器

library ieee;
use ieee.std_logic_1164.all;
entity paddr is 
port(
	X1,X2,X3,X4:in std_logic;
	Y1,Y2,Y3,Y4:in std_logic;
	F1,F2,F3,F4:out std_logic;
	E,C0:in std_logic
);
end paddr;

architecture be of paddr is
signal G1,G2,G3,G4	: std_logic;
signal P1,P2,P3,P4	: std_logic;
signal C1,C2,C3,C4	: std_logic;
begin
	G1 <= X1 and Y1;
	G2 <= X2 and Y2;
	G3 <= X3 and Y3;
	G4 <= X4 and Y4;
	P1 <= X1 or Y1;
	P2 <= X2 or Y2;
	P3 <= X3 or Y3;
	P4 <= X4 or Y4;
	C1 <= G1 or (P1 and C0);
	C2 <= G2 or (P2 and G1) or (P2 and P1 and C0);
	C3 <= G3 or (P3 and G2) or (P3 and P2 and G1) or (P3 and P2 and P1 and C0);
	C4 <= G4 or (P4 and G3) or (P4 and P3 and G2) or (P4 and P3 and P2 and P1 and G1) or (P4 and P3 and P2 and P1 and C0);
	F1 <= (X1 and not (Y1) and not C0) or (not X1 and Y1 and not C0) 
		or (not X1 and not Y1 and C0) or (X1 and Y1 and C0);
	F2 <= (X2 and not (Y2) and not C1) or (not X2 and Y2 and not C1) 
		or (not X2 and not Y2 and C1) or (X2 and Y2 and C1);
	F3 <= (X3 and not (Y3) and not C2) or (not X3 and Y3 and not C2) 
		or (not X3 and not Y3 and C2) or (X3 and Y3 and C2);
	F4 <= (X4 and not (Y4) and not C3) or (not X4 and Y4 and not C3) 
		or (not X4 and not Y4 and C3) or (X4 and Y4 and C3);
end be;

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seg7 is
port(
code: in std_logic_vector(3 downto 0);
seg : out std_logic_vector(7 downto 0)
);
end seg7;

architecture behave of seg7 is
begin
process(code)
begin
 case code is 
		when  "0000" =>
		seg<="11000000";
		when "0001" =>
		seg<="11111001";
		when "0010" =>
		seg<="10100100";
		when "0011"=>
		seg<="10110000";
		when "0100" =>
		seg<="10011001";
		when "0101" =>
		seg <="10010010";
		when "0110" =>
		seg <="10000010";
		when "0111" =>
		seg <= "11111000";
		when "1000" =>
		seg <="10000000";
		when "1001" =>
		seg <="10010000";
		when "1010" =>
		seg <="10001000";
		when "1011" =>
		seg <="10000011";
		when "1100" =>
		seg <="11000110";
		when "1101" =>
		seg <="10100001";
		when "1110" =>
		seg <="10000110";
		when "1111" =>
		seg <="10001110";
		when others =>seg<="11111111";
		end case;
		end process;
 end behave;
 
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
 entity padder is 
 port
 (
	X1,X2,X3,X4	: in std_logic;
	Y1,Y2,Y3,Y4	: in std_logic;
	C0			: in std_logic;
	E			: in std_logic;
	seg1: out std_logic_vector(7 downto 0);
	seg2: out std_logic_vector(7 downto 0);
	seg3: out std_logic_vector(7 downto 0)
 );
 end padder;
 
 architecture be of padder is
 component paddr
 port(
		X1,X2,X3,X4:in std_logic;
		Y1,Y2,Y3,Y4:in std_logic;
		F1,F2,F3,F4:out std_logic;
		E,C0:in std_logic
	);
end component;
component seg7
port(
code: in std_logic_vector(3 downto 0);
seg : out std_logic_vector(7 downto 0)
);
end component;
signal m,mm,mmm:std_logic_vector(3 downto 0);
begin
u1: paddr port map(X1=>X1,X2=>X2,X3=>X3,X4=>X4,Y1=>Y1,Y2=>Y2,Y3=>Y3,Y4=>Y4,C0=>C0,E=>E,F1=>m(0),
F2=>m(1),F3=>m(2),F4=>m(3));
mm <= (X4,X3,X2,X1);
mmm<= (Y4,Y3,Y2,Y1);
u2: seg7 port map(code=>mm,seg=>seg1);
u3: seg7 port map(code=>mmm,seg=>seg2);
u4: seg7 port map(code=>m,seg=>seg3);
end be;