paddr.qsf

4位二进制加法器

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		paddr_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C70F896C6
set_global_assignment -name TOP_LEVEL_ENTITY padder
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:24:02  APRIL 06, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VHDL_FILE paddr.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_AC24 -to X1
set_location_assignment PIN_AC23 -to X2
set_location_assignment PIN_AD24 -to X3
set_location_assignment PIN_AE27 -to X4
set_location_assignment PIN_AB26 -to Y1
set_location_assignment PIN_AB25 -to Y2
set_location_assignment PIN_AC27 -to Y3
set_location_assignment PIN_AC26 -to Y4
set_location_assignment PIN_AA23 -to C0
set_location_assignment PIN_AG13 -to seg1[0]
set_location_assignment PIN_AE16 -to seg1[1]
set_location_assignment PIN_AF16 -to seg1[2]
set_location_assignment PIN_AG16 -to seg1[3]
set_location_assignment PIN_AE17 -to seg1[4]
set_location_assignment PIN_AF17 -to seg1[5]
set_location_assignment PIN_AD17 -to seg1[6]
set_location_assignment PIN_AC17 -to seg1[7]
set_location_assignment PIN_AE8 -to seg2[0]
set_location_assignment PIN_AF9 -to seg2[1]
set_location_assignment PIN_AH9 -to seg2[2]
set_location_assignment PIN_AD10 -to seg2[3]
set_location_assignment PIN_AF10 -to seg2[4]
set_location_assignment PIN_AD11 -to seg2[5]
set_location_assignment PIN_AD12 -to seg2[6]
set_location_assignment PIN_AF12 -to seg2[7]
set_location_assignment PIN_AE7 -to seg3[0]
set_location_assignment PIN_AF7 -to seg3[1]
set_location_assignment PIN_AH5 -to seg3[2]
set_location_assignment PIN_AG4 -to seg3[3]
set_location_assignment PIN_AB18 -to seg3[4]
set_location_assignment PIN_AB19 -to seg3[5]
set_location_assignment PIN_AE19 -to seg3[6]
set_location_assignment PIN_AC19 -to seg3[7]
set_global_assignment -name SIMULATION_MODE FUNCTIONAL