full_adder.fit.rpt

这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序

; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 癈   ;
; High Junction Temperature ; 85 癈  ;
+---------------------------+--------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 3          ;
; LE/ALM Count - Fit Attempt 1                                     ; 3          ;
; LAB Count - Fit Attempt 1                                        ; 2          ;
; Outputs per Lab - Fit Attempt 1                                  ; 1.000      ;
; Inputs per LAB - Fit Attempt 1                                   ; 1.500      ;
; Global Inputs per LAB - Fit Attempt 1                            ; 0.000      ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ; 0:2        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ; 0:2        ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ; 0:2        ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ; 0:2        ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ; 0:2        ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:2        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ; 0:2        ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ; 0:2        ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1          ; 0:2        ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1      ; 0:2        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1        ; 0:2        ;
; LEs in Chains - Fit Attempt 1                                    ; 0          ;
; LEs in Long Chains - Fit Attempt 1                               ; 0          ;
; LABs with Chains - Fit Attempt 1                                 ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                        ; 0          ;
; Time - Fit Attempt 1                                             ; 0          ;
+------------------------------------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Placement                       ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff         ;
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000      ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+--------------------------------------------------+
; Advanced Data - Routing                          ;
+-------------------------------------+------------+
; Name                                ; Value      ;
+-------------------------------------+------------+
; Early Wire Use - Fit Attempt 1      ; 0          ;
; Peak Regional Wire - Fit Attempt 1  ; 0          ;
; Early Slack - Fit Attempt 1         ; 2147483639 ;
; Mid Slack - Fit Attempt 1           ; 2147483639 ;
; Late Slack - Fit Attempt 1          ; 2147483639 ;
; Late Wire Use - Fit Attempt 1       ; 0          ;
; Time - Fit Attempt 1                ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.070      ;
+-------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Nov 04 01:54:27 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off full_adder -c full_adder
Info: Automatically selected device EP2C5T144C6 for design full_adder
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 7 of 7 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C8T144C6 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS41p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 5 pins of 5 total pins
    Info: Pin sum not assigned to an exact location on the device
    Info: Pin cout not assigned to an exact location on the device
    Info: Pin ain not assigned to an exact location on the device
    Info: Pin cin not assigned to an exact location on the device
    Info: Pin bin not assigned to an exact location on the device
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 5 (unused VREF, 3.30 VCCIO, 3 input, 2 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    I