ocldreg.h
来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· C头文件 代码 · 共 504 行 · 第 1/3 页
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504 行
/*****************************************************************************/
/* */
/* PROJECT : ANYSTORE II */
/* MODULE : LLD */
/* NAME : OneNAND Controller Low-level Driver header file */
/* FILE : OCLDReg.h */
/* PURPOSE : Register, Command Set, and Local Definitions for OneNAND */
/* */
/*---------------------------------------------------------------------------*/
/* */
/* COPYRIGHT 2007-2008, SAMSUNG ELECTRONICS CO., LTD. */
/* ALL RIGHTS RESERVED */
/* */
/* Permission is hereby granted to licensees of Samsung Electronics */
/* Co., Ltd. products to use or abstract this computer program for the */
/* sole purpose of implementing NAND/OneNAND based on Samsung */
/* Electronics Co., Ltd. products. No other rights to reproduce, use, */
/* or disseminate this computer program, whether in part or in whole, */
/* are granted. */
/* */
/* Samsung Electronics Co., Ltd. makes no representations or warranties */
/* with respect to the performance of this computer program, and */
/* specifically disclaims any responsibility for any damages, */
/* special or consequential, connected with the use of this program. */
/* */
/*---------------------------------------------------------------------------*/
/* */
/* REVISION HISTORY */
/* */
/* - 06/MARCH/2007 [Yulwon Cho] : First writing */
/* */
/*****************************************************************************/
#ifndef _ONENAND_REGISTER_H_
#define _ONENAND_REGISTER_H_
/*****************************************************************************/
/* OneNAND Base Address Definitions */
/*****************************************************************************/
#define REG_SHIFT 1
#define DAT_SHIFT 2
#define REG_BASE_ADDR(x) ((x) + (0x0001E000>>REG_SHIFT))
/*****************************************************************************/
/* OneNAND Register Address Definitions */
/*****************************************************************************/
#define ONLD_REG_MANUF_ID(x) (REG_BASE_ADDR(x) + (0x0000>>REG_SHIFT))
#define ONLD_REG_DEV_ID(x) (REG_BASE_ADDR(x) + (0x0002>>REG_SHIFT))
#define ONLD_REG_VER_ID(x) (REG_BASE_ADDR(x) + (0x0004>>REG_SHIFT))
#define ONLD_REG_DATABUF_SIZE(x) (REG_BASE_ADDR(x) + (0x0006>>REG_SHIFT))
#define ONLD_REG_BOOTBUF_SIZE(x) (REG_BASE_ADDR(x) + (0x0008>>REG_SHIFT))
#define ONLD_REG_BUF_AMOUNT(x) (REG_BASE_ADDR(x) + (0x000A>>REG_SHIFT))
#define ONLD_REG_TECH(x) (REG_BASE_ADDR(x) + (0x000C>>REG_SHIFT))
#define ONLD_REG_START_ADDR1(x) (REG_BASE_ADDR(x) + (0x0200>>REG_SHIFT))
#define ONLD_REG_START_ADDR2(x) (REG_BASE_ADDR(x) + (0x0202>>REG_SHIFT))
#define ONLD_REG_START_ADDR3(x) (REG_BASE_ADDR(x) + (0x0204>>REG_SHIFT))
#define ONLD_REG_START_ADDR4(x) (REG_BASE_ADDR(x) + (0x0206>>REG_SHIFT))
#define ONLD_REG_START_ADDR5(x) (REG_BASE_ADDR(x) + (0x0208>>REG_SHIFT))
#define ONLD_REG_START_ADDR6(x) (REG_BASE_ADDR(x) + (0x020A>>REG_SHIFT))
#define ONLD_REG_START_ADDR7(x) (REG_BASE_ADDR(x) + (0x020C>>REG_SHIFT))
#define ONLD_REG_START_ADDR8(x) (REG_BASE_ADDR(x) + (0x020E>>REG_SHIFT))
#define ONLD_REG_START_BUF(x) (REG_BASE_ADDR(x) + (0x0400>>REG_SHIFT))
#define ONLD_REG_CMD(x) (REG_BASE_ADDR(x) + (0x0440>>REG_SHIFT))
#define ONLD_REG_SYS_CONF1(x) (REG_BASE_ADDR(x) + (0x0442>>REG_SHIFT))
#define ONLD_REG_SYS_CONF2(x) (REG_BASE_ADDR(x) + (0x0444>>REG_SHIFT))
#define ONLD_REG_CTRL_STAT(x) (REG_BASE_ADDR(x) + (0x0480>>REG_SHIFT))
#define ONLD_REG_INT(x) (REG_BASE_ADDR(x) + (0x0482>>REG_SHIFT))
#define ONLD_REG_ULOCK_START_BA(x) (REG_BASE_ADDR(x) + (0x0498>>REG_SHIFT))
#define ONLD_REG_ULOCK_END_BA(x) (REG_BASE_ADDR(x) + (0x049A>>REG_SHIFT))
#define ONLD_REG_WR_PROTECT_STAT(x) (REG_BASE_ADDR(x) + (0x049C>>REG_SHIFT))
#define ONLD_REG_ECC_STAT(x) (REG_BASE_ADDR(x) + (0x1E00>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_MB0(x) (REG_BASE_ADDR(x) + (0x1E02>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_SB0(x) (REG_BASE_ADDR(x) + (0x1E04>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_MB1(x) (REG_BASE_ADDR(x) + (0x1E06>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_SB1(x) (REG_BASE_ADDR(x) + (0x1E08>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_MB2(x) (REG_BASE_ADDR(x) + (0x1E0A>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_SB2(x) (REG_BASE_ADDR(x) + (0x1E0C>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_MB3(x) (REG_BASE_ADDR(x) + (0x1E0E>>REG_SHIFT))
#define ONLD_REG_ECC_RSLT_SB3(x) (REG_BASE_ADDR(x) + (0x1E10>>REG_SHIFT))
/*****************************************************************************/
/* OneNAND Main Buffer Address */
/*****************************************************************************/
#define ONLD_BT_MB0_ADDR(x) ((x) + (0x00000>>REG_SHIFT))
#define ONLD_BT_MB1_ADDR(x) ((x) + (0x00200>>REG_SHIFT))
#define ONLD_DT_MB00_ADDR(x) ((x) + (0x00400>>REG_SHIFT))
#define ONLD_DT_MB01_ADDR(x) ((x) + (0x00600>>REG_SHIFT))
#define ONLD_DT_MB02_ADDR(x) ((x) + (0x00800>>REG_SHIFT))
#define ONLD_DT_MB03_ADDR(x) ((x) + (0x00A00>>REG_SHIFT))
#define ONLD_DT_MB10_ADDR(x) ((x) + (0x00C00>>REG_SHIFT))
#define ONLD_DT_MB11_ADDR(x) ((x) + (0x00E00>>REG_SHIFT))
#define ONLD_DT_MB12_ADDR(x) ((x) + (0x01000>>REG_SHIFT))
#define ONLD_DT_MB13_ADDR(x) ((x) + (0x01200>>REG_SHIFT))
#define ONLD_BT_SB0_ADDR(x) ((x) + (0x10000>>REG_SHIFT))
#define ONLD_BT_SB1_ADDR(x) ((x) + (0x10010>>REG_SHIFT))
#define ONLD_DT_SB00_ADDR(x) ((x) + (0x10020>>REG_SHIFT))
#define ONLD_DT_SB01_ADDR(x) ((x) + (0x10030>>REG_SHIFT))
#define ONLD_DT_SB02_ADDR(x) ((x) + (0x10040>>REG_SHIFT))
#define ONLD_DT_SB03_ADDR(x) ((x) + (0x10050>>REG_SHIFT))
#define ONLD_DT_SB10_ADDR(x) ((x) + (0x10060>>REG_SHIFT))
#define ONLD_DT_SB11_ADDR(x) ((x) + (0x10070>>REG_SHIFT))
#define ONLD_DT_SB12_ADDR(x) ((x) + (0x10080>>REG_SHIFT))
#define ONLD_DT_SB13_ADDR(x) ((x) + (0x10090>>REG_SHIFT))
/*****************************************************************************/
/* OneNAND Register Address Definitions */
/*****************************************************************************/
#define OCLD_REG_BASE 0x4b800000 // OCLD_M11_REGu32 Flash Controller Base Address
#define OCLD_M00_BASE(x) (x) // Map 00 Base Address. BufferRAM access
#define OCLD_M01_BASE(x) ((x) + 0x04000000) // Map 01 Base Address. DMA
#define OCLD_M10_BASE(x) ((x) + 0x08000000) // Map 10 Base Address. Commands
#define OCLD_M11_BASE(x) ((x) + 0x0c000000) // Map 11 Base Address. ONL Direct access
/******************************************************************************
OneNANC Control Register Address Map
*******************************************************************************/
#define REGu32(x) *(volatile UINT32 *)(x)
#define OCLD_REG_MEM_CFG(n) (*(volatile UINT32*)(n + 0x0))
#define BIT_ECC (1<<8)
#define BIT_RDYPOL (1<<7)
#define BIT_INTPOL (1<<6)
#define BIT_IOBE (1<<5)
#define OCLD_REG_BURST_LEN(n) (*(volatile UINT32*)(n + 0x10))
#define BL_4WORDS 4
#define BL_8WORDS 8
#define BL_16WORDS 16
#define BL_32WORDS 32
#define OCLD_REG_MEM_RESET(n) (*(volatile UINT32*)(n + 0x20))
#define WARMRESET (1)
#define CORERESET (2)
#define HOTRESET (3)
#define OCLD_REG_INT_ERR_STAT(n) (*(volatile UINT32*)(n + 0x30))
#define OCLD_REG_INT_ERR_MASK(n) (*(volatile UINT32*)(n + 0x40))
#define OCLD_REG_INT_ERR_ACK(n) (*(volatile UINT32*)(n + 0x50))
#define BIT_CACHE_OP_ERR (1<<13)
#define BIT_RST_CMP (1<<12)
#define BIT_RDY_ACT (1<<11)
#define BIT_INT_ACT (1<<10)
#define BIT_UNSUP_CMD (1<<9)
#define BIT_LOCKED_BLK (1<<8)
#define BIT_BLK_RW_CMP (1<<7)
#define BIT_ERS_CMP (1<<6)
#define BIT_PGM_CMP (1<<5)
#define BIT_LOAD_CMP (1<<4)
#define BIT_ERS_FAIL (1<<3)
#define BIT_PGM_FAIL (1<<2)
#define BIT_INT_TO (1<<1)
#define BIT_LD_FAIL_ECC_ERR (1<<0)
#define OCLD_REG_ECC_ERR_STAT(n) (*(volatile UINT32*)(n + 0x60))
#define OCLD_REG_MANUFACT_ID(n) (*(volatile UINT32*)(n + 0x70))
#define OCLD_REG_DEVICE_ID(n) (*(volatile UINT32*)(n + 0x80))
#define OCLD_REG_DATA_BUF_SIZE(n) (*(volatile UINT32*)(n + 0x90))
#define OCLD_REG_BOOT_BUF_SIZE(n) (*(volatile UINT32*)(n + 0xA0))
#define OCLD_REG_BUF_AMOUNT(n) (*(volatile UINT32*)(n + 0xB0))
#define OCLD_REG_TECH(n) (*(volatile UINT32*)(n + 0xC0))
#define OCLD_REG_FBA_WIDTH(n) (*(volatile UINT32*)(n + 0xD0))
#define OCLD_REG_FPA_WIDTH(n) (*(volatile UINT32*)(n + 0xE0))
#define OCLD_REG_FSA_WIDTH(n) (*(volatile UINT32*)(n + 0xF0))
#define OCLD_REG_REVISION(n) (*(volatile UINT32*)(n + 0x100))
#define OCLD_REG_DATARAM0(n) (*(volatile UINT32*)(n + 0x110))
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