ocldreg.h
来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· C头文件 代码 · 共 504 行 · 第 1/3 页
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#define OCLD_REG_DATARAM1(n) (*(volatile UINT32*)(n + 0x120))
#define OCLD_REG_SYNC_MODE(n) (*(volatile UINT32*)(n + 0x130))
#define OCLD_ASYNC 0
#define OCLD_SYNC 1
#define OCLD_REG_TRANS_SPARE(n) (*(volatile UINT32*)(n + 0x140))
#define TSRF_DATA_ONLY 0
#define TSRF_DATA_SPARE 1
#define OCLD_REG_LOCK_BIT(n) (*(volatile UINT32*)(n + 0x150)) // spec-out, not used.
#define OCLD_REG_DBS_DFS_WIDTH(n) (*(volatile UINT32*)(n + 0x160))
#define OCLD_REG_PAGE_CNT(n) (*(volatile UINT32*)(n + 0x170))
#define OCLD_REG_ERR_PAGE_ADDR(n) (*(volatile UINT32*)(n + 0x180))
#define OCLD_REG_BURST_RD_LAT(n) (*(volatile UINT32*)(n + 0x190))
#define OCLD_REG_INT_PIN_ENABLE(n) (*(volatile UINT32*)(n + 0x1A0))
#define USE_STATUS_REG 0
#define USE_INT_PIN 1
#define OCLD_REG_INT_MON_CYC(n) (*(volatile UINT32*)(n + 0x1B0))
#define OCLD_REG_ACC_CLOCK(n) (*(volatile UINT32*)(n + 0x1C0))
#define OCLD_REG_SLOW_RD_PATH(n) (*(volatile UINT32*)(n + 0x1D0))
#define OCLD_REG_ERR_BLK_ADDR(n) (*(volatile UINT32*)(n + 0x1E0))
#define OCLD_REG_FLASH_VER_ID(n) (*(volatile UINT32*)(n + 0x1F0))
#define OCLD_REG_FLASH_AUX_CNTRL(n) (*(volatile UINT32*)(n + 0x300)) // added on S3C6410
#define OCLD_REG_FLASH_AFIFO_CNT(n) (*(volatile UINT32*)(n + 0x310)) // added on S3C6410
/******************************************************************************
OneNANC Control MAP11 Register Address Map
*******************************************************************************/
#define OCLD_M11_REG_BASE(x) (OCLD_M11_BASE(x) + 0x3C000) // Registers OCLD_SPARE_SIZE Base Address
#define OCLD_M11_REG_MANUF_ID(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0000) // Manufaturer identification
#define OCLD_M11_REG_DEV_ID(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0004) // Device identification
#define OCLD_M11_REG_VER_ID(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0008) // N/A
#define OCLD_M11_REG_DATABUF_SIZE(x) REGu32(OCLD_M11_REG_BASE(x) + 0x000C) // Data buffer size (in Words)
#define DATABUFSIZE 0x0800 // 4KB
#define OCLD_M11_REG_BOOTBUF_SIZE(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0010) // Boot buffer size (in Words)
#define BOOTBUFSIZE 0x0200 // 1KB
#define OCLD_M11_REG_BUF_AMOUNT(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0014) // Amount of data/boot buffers
#define DATABUFAMOUNT 2
#define BOOTBUFAMOUNT 1
#define BUFAMOUNT ((DATABUFAMOUNT << 8) + BOOTBUFAMOUNT)
#define OCLD_M11_REG_TECH(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0018) // Info about technology
#define NAND_SLC 0x0000
#define NAND_MLC 0x0001
#define OCLD_M11_REG_START_ADDR1(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0400) // Chip address for selection of NAND. Core in DDP & Block address
#define OCLD_M11_REG_START_ADDR2(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0404) // Chip address for selection of BufferRAM in DDP
#define OCLD_M11_REG_START_ADDR3(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0408) // Destination Block address for Copy back program
#define OCLD_M11_REG_START_ADDR4(x) REGu32(OCLD_M11_REG_BASE(x) + 0x040C) // Destination Page & OCLD_MAIN_SIZE address for Copy back program
#define OCLD_M11_REG_START_ADDR5(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0410) // N/A
#define OCLD_M11_REG_START_ADDR6(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0414) // N/A
#define OCLD_M11_REG_START_ADDR7(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0418) // N/A
#define OCLD_M11_REG_START_ADDR8(x) REGu32(OCLD_M11_REG_BASE(x) + 0x041C) // NAND Flash Page & OCLD_MAIN_SIZE address
#define OCLD_M11_REG_START_BUF(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0800) // Buffer Number for the page data transfer to/from the memory and the start Buffer Address
#define BOOTRAM_0 0x0000
#define BOOTRAM_1 0x0100
#define DATARAM_00 0x0800
#define DATARAM_01 0x0900
#define DATARAM_02 0x0A00
#define DATARAM_03 0x0B00
#define DATARAM_10 0x0C00
#define DATARAM_11 0x0D00
#define DATARAM_12 0x0E00
#define DATARAM_13 0x0F00
#define ONE_SECTOR 1
#define TWO_SECTOR 2
#define THREE_SECTOR 3
#define FOUR_SECTOR 0
#define OCLD_M11_REG_CMD(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0880) // Host control and memory operatin commands
#define LOAD_SECTORS 0x0000
#define LOAD_SPARES 0x0013
#define PROGRAM_SECTORS 0x0080
#define PROGRAM_SPARES 0x001A
#define COPY_BACK_PROGRAM 0x001B
#define UNLOCK_BLOCK 0x0023
#define LOCK_BLOCK 0x002A
#define LOCK_TIGHT_BLOCK 0x002C
#define ERASE_VERIFY_READ 0x0071
#define BLOCK_ERASE 0x0094
#define MULTI_BLOCK_ERASE 0x0095
#define ERASE_SUSPEND 0x00B0
#define ERASE_RESUME 0x0030
#define RESET_NAND_CORE 0x00F0
#define RESET_MuxOneNAND 0x00F3
#define OTP_ACCESS 0x0065
#define OCLD_M11_REG_SYS_CONF1(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0884) // memory and Host Interface Configuration
#define RM_ASYNC_READ 0x0000 // Read Mode
#define RM_SYNC_READ 0x8000
#define BRL_8 0x0000 // Burst Read Latency Cycles 8 (N/A)
#define BRL_9 0x1000 // Burst Read Latency Cycles 9 (N/A)
#define BRL_10 0x2000 // Burst Read Latency Cycles 10 (N/A)
#define BRL_3 0x3000 // Burst Read Latency Cycles 3
#define BRL_4 0x4000 // Burst Read Latency Cycles 4 (Default)
#define BRL_5 0x5000 // Burst Read Latency Cycles 5
#define BRL_6 0x6000 // Burst Read Latency Cycles 6
#define BRL_7 0x7000 // Burst Read Latency Cycles 7
#define BL_CONT 0x0000 // Burst Length Continuous (Default)
#define BL_4 0x0200 // Burst Length 4 Words
#define BL_8 0x0400 // Burst Length 8 Words
#define BL_16 0x0600 // Burst Length 16 Words
#define BL_32 0x0800 // Burst Length 32 Words (N/A)
#define ECC 0x0000 // Error Correction Code
#define ECC_BYPASS 0x0100
#define RDY_ACTIVE_HIGH 0x0080 // RDY Polarity
#define RDY_ACTIVE_LOW 0x0000
#define INT_ACTIVE_HIGH 0x0040 // INT Polarity
#define INT_ACTIVE_LOW 0x0000
#define IOBE_ENABLE 0x0020 // IOBE(I/O Buffer Enable)
#define IOBE_DISABLE 0x0000
#define RDY_ACTIVE_BEFORE 0x0010 // RDY Configuration
#define RDY_ACTIVE_WITH 0x0000
#define WM_SYNC_WRITE 0x0002 // Write Mode
#define WM_ASYNC_WRITE 0x0000 // Write Mode
#define BWPS_UNLOCKED 0x0001 // Boot Buffer Write Protect Status
#define BWPS_LOCKED 0x0000
#define OCLD_M11_REG_SYS_CONF2(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0888) // N/A
#define OCLD_M11_REG_CTRL_STAT(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0900) // Controller Status and result of memory operation
#define CTRL_ONGO 0x8000 // 0: ready, 1: busy
#define LOCK_STATE 0x4000 // 0: unlocked, 1: locked
#define LOAD_STATE 0x2000 // 0: ready, 1: busy or error
#define PROG_STATE 0x1000 // 0: ready, 1: busy or error
#define ERASE_STATE 0x0800 // 0: ready, 1: busy or error
#define ERROR_STATE 0x0400 // 0: pass, 1: fail
#define SUSPEND_STATE 0x0200 // 0: erase resume, 1: erase suspend, program ongoing, load ongoing, program fail, load fail, invalid command
#define RESET_STATE 0x0080 // 0: ready, 1: busy
#define OTPL_STATE 0x0040 // 0: OPT unlocked, 1: OPT locked
#define TIME_OUT 0x0001 // 0: no time out (fixed)
#define PROG_LOCK (LOCK_STATE | PROG_STATE | ERROR_STATE)
#define ERASE_LOCK (LOCK_STATE | ERASE_STATE | ERROR_STATE)
#define PROG_FAIL (PROG_STATE | ERROR_STATE)
#define ERASE_FAIL (ERASE_STATE | ERROR_STATE)
#define OCLD_M11_REG_INT REGu32(OCLD_M11_REG_BASE(x) + 0x0904) // Memory Command Completion Interrupt Status
#define INT_MASTER 0x8000 // Interrupt
#define INT_RI 0x0080 // Read Interrupt
#define INT_WI 0x0040 // Write Interrupt
#define INT_EI 0x0020 // Erase Interrupt
#define INT_RSTI 0x0010 // Reset Interrupt
#define CLEAR_ALL_INT 0x0000 // Clear Interrupt
#define OCLD_M11_REG_ULOCK_START_BA(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0930) // Start memory block address in Write Protection mode
#define OCLD_M11_REG_ULOCK_END_BA(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0934) // End memory block address in Write Protection mode
#define OCLD_M11_REG_WR_PROTECT_STAT(x) REGu32(OCLD_M11_REG_BASE(x) + 0x0938) // Current memory Write Protection status (unlocked/locked/tight-locked)
#define US 0x0004 // 1: Unlocked
#define LS 0x0002 // 1: Locked
#define LTS 0x0001 // 1: Tight-locked
#define OCLD_M11_REG_ECC_STAT(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C00) // ECC status of OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_M0(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C04) // ECC error position of Main area data error for first selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_S0(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C08) // ECC error position of OCLD_SPARE_SIZE area data error for first selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_M1(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C0C) // ECC error position of Main area data error for second selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_S1(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C10) // ECC error position of OCLD_SPARE_SIZE area data error for second selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_M2(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C14) // ECC error position of Main area data error for third selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_S2(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C18) // ECC error position of OCLD_SPARE_SIZE area data error for third selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_M3(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C1C) // ECC error position of Main area data error for fourth selected OCLD_MAIN_SIZE
#define OCLD_M11_REG_ECC_RES_S3(x) REGu32(OCLD_M11_REG_BASE(x) + 0x3C20) // ECC error position of OCLD_SPARE_SIZE area data error for fourth selected OCLD_MAIN_SIZE
/*****************************************************************************/
/* OneNAND Register Masking values */
/*****************************************************************************/
#define MASK_DFS 0x8000
#define MASK_FBA 0x7FFF
#define MASK_DBS 0x8000
#define MASK_FCBA 0x7FFF
#define MASK_FCPA 0x00FC
#define MASK_FCSA 0x0003
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