ocldreg.h

来自「SAMSUNG S3C6410 CPU BSP for winmobile6」· C头文件 代码 · 共 504 行 · 第 1/3 页

#define MASK_FPA                       0x00FC
#define MASK_BSA                       0x0F00
#define MASK_BSC                       0x0003
#define MASK_FPC                       0x00FF


/*****************************************************************************/
/* OneNAND Main Buffer Address                                               */
/*****************************************************************************/
#define OCLD_M11_ADDR_RATIO          2
#define OCLD_M11_BT_MB0_ADDR(x)     (OCLD_M11_BASE(x) + 0x00000 * OCLD_M11_ADDR_RATIO)
#define OCLD_M11_BT_MB1_ADDR(x)     (OCLD_M11_BASE(x) + 0x00200 * OCLD_M11_ADDR_RATIO)
#define OCLD_M11_DT_MB00_ADDR(x)    (OCLD_M11_BASE(x) + 0x00400 * OCLD_M11_ADDR_RATIO)

#define OCLD_M11_BT_SB0_ADDR(x)     (OCLD_M11_BASE(x) + 0x10000 * OCLD_M11_ADDR_RATIO)
#define OCLD_M11_BT_SB1_ADDR(x)     (OCLD_M11_BASE(x) + 0x10010 * OCLD_M11_ADDR_RATIO)
#define OCLD_M11_DT_SB00_ADDR(x)    (OCLD_M11_BASE(x) + 0x10020 * OCLD_M11_ADDR_RATIO)

/******************************************************************************
  OneNAND MAP10 Register Command Set
*******************************************************************************/
#define OCLD_CMD10_ERASE_STAT        0x0000  // Save erase status to memory controller
    #define INPROGRESS              1
#define OCLD_CMD10_ERASE_MBLKS       0x0001  // Save block address for multi-block erase
#define OCLD_CMD10_ERASE_BLK         0x0003  // Save block address for single-block or the final block of a multi-block erase and initiate the erase
#define OCLD_CMD10_ULOCK_START_BLK   0x0008  // Set unlock start address
#define OCLD_CMD10_ULOCK_END_BLK_RUN 0x0009  // Set unlock end address and initiate the unlock
#define OCLD_CMD10_LOCK_START_BLK    0x000A  // Set lock start address
#define OCLD_CMD10_LOCK_END_BLK_RUN  0x000B  // Set lock end address and initiate the lock
#define OCLD_CMD10_LOCKT_START_BLK   0x000C  // Set lock-tight start address
#define OCLD_CMD10_LOCKT_END_BLK_RUN 0x000D  // Set lock-tight end address and initiate the lock
#define OCLD_CMD10_ULOCK_ALL_BLKS    0x000E  // Unlock the entire memory array
#define OCLD_CMD10_RMW_LOAD_BUF      0x0010  // Load page to map 00 XIP buffer
#define OCLD_CMD10_RMW_PROGRAM_BUF   0x0011  // Write map 00 XIP buffer to memory
#define OCLD_CMD10_ACCESS_OTP        0x0012  // Setup for OTP access
#define OCLD_CMD10_ACCESS_SPARE      0x0013  // Setup for OCLD_SPARE_SIZE area access
#define OCLD_CMD10_ACCESS_MAIN       0x0014  // Setup for main area access
#define OCLD_CMD10_ERASE_VERIFY      0x0015  // Verify erase block
#define OCLD_CMD10_CPBACK_SRC        0x1000  // Set copy source address
#define OCLD_CMD10_CPBACK_DST        0x2000  // Set copy destination address and initiate copy of PP pages
#define OCLD_CMD10_PRE_READ          0x4000  // Setup pre-read of PP pages
#define OCLD_CMD10_PRE_WRITE         0x4100  // Setup pre-write of PP pages    

/*****************************************************************************/
/* OneNAND System Configureation1 Register Values                            */
/*****************************************************************************/
#define SYNC_READ_MODE              0x8000
#define ASYNC_READ_MODE             0x0000

#define BST_RD_LATENCY_8            0x0000      /*   N/A   */
#define BST_RD_LATENCY_9            0x1000      /*   N/A   */
#define BST_RD_LATENCY_10           0x2000      /*   N/A   */
#define BST_RD_LATENCY_3            0x3000      /*   min   */
#define BST_RD_LATENCY_4            0x4000      /* default */
#define BST_RD_LATENCY_5            0x5000      
#define BST_RD_LATENCY_6            0x6000
#define BST_RD_LATENCY_7            0x7000

#define BST_LENGTH_CONT             0x0000      /* default */
#define BST_LENGTH_4WD              0x0200
#define BST_LENGTH_8WD              0x0400
#define BST_LENGTH_16WD             0x0600
#define BST_LENGTH_32WD             0x0800      /* N/A on spare */
#define BST_LENGTH_1KWD             0x0A00      /* N/A on spare, sync. burst block read only */

#define CONF1_ECC_ON                0xFEFF
#define CONF1_ECC_OFF               0x0100      //(~CONF1_ECC_ON)   //0x0100

#define RDY_POLAR                   0x0080
#define INT_POLAR                   0x0040
#define IOBE_ENABLE                 0x0020

#define BWPS_UNLOCKED               0x0001

#define HF_ON                0x0004
#define HF_OFF               0xFFFB
#define RDY_CONF             0x0010

/*****************************************************************************/
/* OneNAND Controller Status Register Values                                 */
/*****************************************************************************/
#define CTRL_ONGO                   0x8000
#define LOCK_STATE                  0x4000
#define LOAD_STATE                  0x2000
#define PROG_STATE                  0x1000
#define ERASE_STATE					0x0800
#define ERROR_STATE					0x0400
#define SUSPEND_STATE				0x0200
#define RESET_STATE					0x0080
#define OTPL_STATE					0x0040
#define TIME_OUT                    0x0001

#define PROG_LOCK					(LOCK_STATE | PROG_STATE | ERROR_STATE)
#define ERASE_LOCK					(LOCK_STATE | ERASE_STATE | ERROR_STATE)
#define PROG_FAIL					(PROG_STATE | ERROR_STATE)
#define ERASE_FAIL					(ERASE_STATE | ERROR_STATE)

/*****************************************************************************/
/* OneNAND Controller Interrupt Status Register Values                       */
/*****************************************************************************/
#define CINT_CLEAR                   0x0000
#define CINT_MASK                    0xFFFF

#define CPEND_INT                    (BIT_INT_ACT)
#define CPEND_READ                   (BIT_INT_ACT | BIT_BLK_RW_CMP | BIT_LOAD_CMP)
#define CPEND_WRITE                  (BIT_INT_ACT | BIT_BLK_RW_CMP | BIT_PGM_CMP)
#define CPEND_ERASE                  (BIT_INT_ACT | BIT_ERS_CMP)
#define CPEND_RESET                  (BIT_INT_ACT | BIT_RST_CMP)
#define CPEND_LOAD                   (BIT_INT_ACT | BIT_LOAD_CMP)

/*****************************************************************************/
/* OneNAND ECC Status Register Valuies                                       */
/*****************************************************************************/
#define ECC_SB0_NO_ERR              0x0000
#define ECC_SB0_1BIT_ERR            0x0001
#define ECC_SB0_2BIT_ERR            0x0002
#define ECC_MB0_NO_ERR              0x0000
#define ECC_MB0_1BIT_ERR            0x0004
#define ECC_MB0_2BIT_ERR            0x0008

#define ECC_SB1_NO_ERR              0x0000
#define ECC_SB1_1BIT_ERR            0x0010
#define ECC_SB1_2BIT_ERR            0x0020
#define ECC_MB1_NO_ERR              0x0000
#define ECC_MB1_1BIT_ERR            0x0040
#define ECC_MB1_2BIT_ERR            0x0080

#define ECC_SB2_NO_ERR              0x0000
#define ECC_SB2_1BIT_ERR            0x0100
#define ECC_SB2_2BIT_ERR            0x0200
#define ECC_MB2_NO_ERR              0x0000
#define ECC_MB2_1BIT_ERR            0x0400
#define ECC_MB2_2BIT_ERR            0x0800

#define ECC_SB3_NO_ERR              0x0000
#define ECC_SB3_1BIT_ERR            0x1000
#define ECC_SB3_2BIT_ERR            0x2000
#define ECC_MB3_NO_ERR              0x0000
#define ECC_MB3_1BIT_ERR            0x4000
#define ECC_MB3_2BIT_ERR            0x8000

#define ECC_ANY_2BIT_ERR            0xAAAA
#define ECC_ANY_BIT_ERR             0xFFFF
#define ECC_MAIN_BIT_ERR            0xCCCC
#define ECC_SPARE_BIT_ERR           0x3333
#define ECC_REG_CLEAR               0x0000


/*****************************************************************************/
/* OneNAND Misc Values                                                       */
/*****************************************************************************/
#define SECTOR0                     0x0000
#define SECTOR1                     0x0001
#define SECTOR2                     0x0002
#define SECTOR3                     0x0003

#define DATA_BUF0                   0x0000
#define DATA_BUF1                   0x0001

#define SECTOR0_OFFSET              0x0000
#define SECTOR1_OFFSET              0x0200
#define SECTOR2_OFFSET              0x0400
#define SECTOR3_OFFSET              0x0600

#define VALID_BLK_MARK              0xFFFF

#endif /* _ONENAND_REGISTER_H_ */