yibu_control.hier_info

分别完成了异步发送电路

|yibu_control
rst => receiver:a2.rst
rst => trans_port:a1.rst
start_write => trans_port:a1.start_write
clk => receiver:a2.clk
clk => trans_port:a1.clk
ETBE => trans_port:a1.ETBE
ERBF => receiver:a2.ERBF
din[0] => trans_port:a1.din[0]
din[1] => trans_port:a1.din[1]
din[2] => trans_port:a1.din[2]
din[3] => trans_port:a1.din[3]
din[4] => trans_port:a1.din[4]
din[5] => trans_port:a1.din[5]
din[6] => trans_port:a1.din[6]
din[7] => trans_port:a1.din[7]
IRQ <= trans_port:a1.IRQ
sout <= trans_port:a1.sout
dout[0] <= receiver:a2.dout[0]
dout[1] <= receiver:a2.dout[1]
dout[2] <= receiver:a2.dout[2]
dout[3] <= receiver:a2.dout[3]
dout[4] <= receiver:a2.dout[4]
dout[5] <= receiver:a2.dout[5]
dout[6] <= receiver:a2.dout[6]
dout[7] <= receiver:a2.dout[7]
data_ready <= receiver:a2.data_ready
overrun_error <= receiver:a2.overrun_error
framing_error <= receiver:a2.framing_error
parity_error <= receiver:a2.parity_error
IQR <= receiver:a2.IQR


|yibu_control|trans_port:a1
rst => tmp1[0].ACLR
rst => tmp1[1].ACLR
rst => tmp1[2].ACLR
rst => tmp1[3].ACLR
rst => temp[0].ACLR
rst => temp[1].ACLR
rst => temp[2].ACLR
rst => temp[3].ACLR
rst => temp[4].ACLR
rst => temp[5].ACLR
rst => temp[6].ACLR
rst => temp[7].ACLR
rst => temp[8].ACLR
rst => temp[9].ACLR
rst => clkdiv[0].ACLR
rst => clkdiv[1].ACLR
rst => clkdiv[2].ACLR
rst => clkdiv[3].ACLR
rst => clkdiv[4].ACLR
rst => clkdiv[5].ACLR
rst => sout~reg0.ACLR
rst => IRQ~reg0.ACLR
rst => TBE.PRESET
rst => tbr[0].ACLR
rst => tbr[1].ACLR
rst => tbr[2].ACLR
rst => tbr[3].ACLR
rst => tbr[4].ACLR
rst => tbr[5].ACLR
rst => tbr[6].ACLR
rst => tbr[7].ACLR
rst => tsr[0].ACLR
rst => tsr[1].ACLR
rst => tsr[2].ACLR
rst => tsr[3].ACLR
rst => tsr[4].ACLR
rst => tsr[5].ACLR
rst => tsr[6].ACLR
rst => tsr[7].ACLR
start_write => TBE~4.OUTPUTSELECT
start_write => tsr~0.OUTPUTSELECT
start_write => tsr~1.OUTPUTSELECT
start_write => tsr~2.OUTPUTSELECT
start_write => tsr~3.OUTPUTSELECT
start_write => tsr~4.OUTPUTSELECT
start_write => tsr~5.OUTPUTSELECT
start_write => tsr~6.OUTPUTSELECT
start_write => tsr~7.OUTPUTSELECT
start_write => temp~47.OUTPUTSELECT
start_write => temp~48.OUTPUTSELECT
start_write => temp~49.OUTPUTSELECT
start_write => temp~50.OUTPUTSELECT
start_write => temp~51.OUTPUTSELECT
start_write => temp~52.OUTPUTSELECT
start_write => temp~53.OUTPUTSELECT
start_write => temp~54.OUTPUTSELECT
start_write => temp~55.OUTPUTSELECT
start_write => temp~56.OUTPUTSELECT
start_write => IRQ~1.OUTPUTSELECT
start_write => clkdiv~18.OUTPUTSELECT
start_write => clkdiv~19.OUTPUTSELECT
start_write => clkdiv~20.OUTPUTSELECT
start_write => clkdiv~21.OUTPUTSELECT
start_write => clkdiv~22.OUTPUTSELECT
start_write => clkdiv~23.OUTPUTSELECT
start_write => sout~4.OUTPUTSELECT
start_write => tmp1~16.OUTPUTSELECT
start_write => tmp1~17.OUTPUTSELECT
start_write => tmp1~18.OUTPUTSELECT
start_write => tmp1~19.OUTPUTSELECT
clk => tmp1[0].CLK
clk => tmp1[1].CLK
clk => tmp1[2].CLK
clk => tmp1[3].CLK
clk => temp[0].CLK
clk => temp[1].CLK
clk => temp[2].CLK
clk => temp[3].CLK
clk => temp[4].CLK
clk => temp[5].CLK
clk => temp[6].CLK
clk => temp[7].CLK
clk => temp[8].CLK
clk => temp[9].CLK
clk => clkdiv[0].CLK
clk => clkdiv[1].CLK
clk => clkdiv[2].CLK
clk => clkdiv[3].CLK
clk => clkdiv[4].CLK
clk => clkdiv[5].CLK
clk => sout~reg0.CLK
clk => IRQ~reg0.CLK
clk => TBE.CLK
clk => tbr[0].CLK
clk => tbr[1].CLK
clk => tbr[2].CLK
clk => tbr[3].CLK
clk => tbr[4].CLK
clk => tbr[5].CLK
clk => tbr[6].CLK
clk => tbr[7].CLK
clk => tsr[0].CLK
clk => tsr[1].CLK
clk => tsr[2].CLK
clk => tsr[3].CLK
clk => tsr[4].CLK
clk => tsr[5].CLK
clk => tsr[6].CLK
clk => tsr[7].CLK
ETBE => IRQ~0.DATAB
ETBE => clkdiv~6.OUTPUTSELECT
ETBE => clkdiv~7.OUTPUTSELECT
ETBE => clkdiv~8.OUTPUTSELECT
ETBE => clkdiv~9.OUTPUTSELECT
ETBE => clkdiv~10.OUTPUTSELECT
ETBE => clkdiv~11.OUTPUTSELECT
ETBE => sout~2.OUTPUTSELECT
ETBE => temp~27.OUTPUTSELECT
ETBE => temp~28.OUTPUTSELECT
ETBE => temp~29.OUTPUTSELECT
ETBE => temp~30.OUTPUTSELECT
ETBE => temp~31.OUTPUTSELECT
ETBE => temp~32.OUTPUTSELECT
ETBE => temp~33.OUTPUTSELECT
ETBE => temp~34.OUTPUTSELECT
ETBE => temp~35.OUTPUTSELECT
ETBE => temp~36.OUTPUTSELECT
ETBE => tmp1~8.OUTPUTSELECT
ETBE => tmp1~9.OUTPUTSELECT
ETBE => tmp1~10.OUTPUTSELECT
ETBE => tmp1~11.OUTPUTSELECT
ETBE => TBE~2.OUTPUTSELECT
din[0] => tbr~7.DATAB
din[1] => tbr~6.DATAB
din[2] => tbr~5.DATAB
din[3] => tbr~4.DATAB
din[4] => tbr~3.DATAB
din[5] => tbr~2.DATAB
din[6] => tbr~1.DATAB
din[7] => tbr~0.DATAB
IRQ <= IRQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
sout <= sout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|yibu_control|receiver:a2
rst => OE.ACLR
rst => comb~1.OUTPUTSELECT
rst => comb~2.OUTPUTSELECT
rst => comb~3.OUTPUTSELECT
rst => comb~4.OUTPUTSELECT
rst => comb~5.OUTPUTSELECT
rst => comb~6.OUTPUTSELECT
rst => comb~7.OUTPUTSELECT
rst => comb~8.OUTPUTSELECT
rst => comb~9.OUTPUTSELECT
rst => comb~10.OUTPUTSELECT
rst => IRQr.ACLR
rst => LDRB.ACLR
rst => cnt[0].ACLR
rst => cnt[1].ACLR
rst => cnt[2].ACLR
rst => cnt[3].ACLR
rst => PE.ACLR
rst => FE.ACLR
rst => rbr[0].ACLR
rst => rbr[1].ACLR
rst => rbr[2].ACLR
rst => rbr[3].ACLR
rst => rbr[4].ACLR
rst => rbr[5].ACLR
rst => rbr[6].ACLR
rst => rbr[7].ACLR
rst => rsr[0].ACLR
rst => rsr[1].ACLR
rst => rsr[2].ACLR
rst => rsr[3].ACLR
rst => rsr[4].ACLR
rst => rsr[5].ACLR
rst => rsr[6].ACLR
rst => rsr[7].ACLR
rst => count[0].ACLR
rst => count[1].ACLR
rst => count[2].ACLR
rst => count[3].ACLR
rst => count[4].ACLR
rst => clkdiv[0].ACLR
rst => clkdiv[1].ACLR
rst => clkdiv[2].ACLR
rst => clkdiv[3].ACLR
rst => clkdiv[4].ACLR
rst => clkdiv[5].ACLR
rst => dout[0]~reg0.ACLR
rst => dout[1]~reg0.ACLR
rst => dout[2]~reg0.ACLR
rst => dout[3]~reg0.ACLR
rst => dout[4]~reg0.ACLR
rst => dout[5]~reg0.ACLR
rst => dout[6]~reg0.ACLR
rst => dout[7]~reg0.ACLR
rst => data_ready~reg0.ACLR
rst => RBF.ACLR
rst => Rx_State~18.IN1
clk => clklx.CLK
clk => clkcnt[0].CLK
clk => clkcnt[1].CLK
clk => clkcnt[2].CLK
clk => clkcnt[3].CLK
clk => clkcnt[4].CLK
clk => OE.CLK
clk => shift[0].CLK
clk => shift[1].CLK
clk => shift[2].CLK
clk => shift[3].CLK
clk => shift[4].CLK
clk => shift[5].CLK
clk => shift[6].CLK
clk => shift[7].CLK
clk => shift[8].CLK
clk => shift[9].CLK
clk => IRQr.CLK
clk => LDRB.CLK
clk => cnt[0].CLK
clk => cnt[1].CLK
clk => cnt[2].CLK
clk => cnt[3].CLK
clk => PE.CLK
clk => FE.CLK
clk => rbr[0].CLK
clk => rbr[1].CLK
clk => rbr[2].CLK
clk => rbr[3].CLK
clk => rbr[4].CLK
clk => rbr[5].CLK
clk => rbr[6].CLK
clk => rbr[7].CLK
clk => rsr[0].CLK
clk => rsr[1].CLK
clk => rsr[2].CLK
clk => rsr[3].CLK
clk => rsr[4].CLK
clk => rsr[5].CLK
clk => rsr[6].CLK
clk => rsr[7].CLK
clk => count[0].CLK
clk => count[1].CLK
clk => count[2].CLK
clk => count[3].CLK
clk => count[4].CLK
clk => clkdiv[0].CLK
clk => clkdiv[1].CLK
clk => clkdiv[2].CLK
clk => clkdiv[3].CLK
clk => clkdiv[4].CLK
clk => clkdiv[5].CLK
clk => dout[0]~reg0.CLK
clk => dout[1]~reg0.CLK
clk => dout[2]~reg0.CLK
clk => dout[3]~reg0.CLK
clk => dout[4]~reg0.CLK
clk => dout[5]~reg0.CLK
clk => dout[6]~reg0.CLK
clk => dout[7]~reg0.CLK
clk => data_ready~reg0.CLK
clk => RBF.CLK
clk => Rx_State~17.IN1
rxd => comb~0.IN0
rxd => Selector5.IN3
rxd => Rx_State~4.OUTPUTSELECT
rxd => Rx_State~5.OUTPUTSELECT
rxd => Rx_State~6.OUTPUTSELECT
rxd => Rx_State~7.OUTPUTSELECT
rxd => shift~9.DATAB
ERBF => process0~9.IN0
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
data_ready <= data_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= OE.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= FE.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= PE.DB_MAX_OUTPUT_PORT_TYPE
clk46 <= clklx.DB_MAX_OUTPUT_PORT_TYPE
IQR <= IRQr.DB_MAX_OUTPUT_PORT_TYPE