yibu_control.vhd

来自「分别完成了异步发送电路」· VHDL 代码 · 共 50 行

--总的顶层文件构成异步通信控制器。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity yibu_control is
 port (rst,start_write,clk,ETBE,ERBF: in std_logic ;
       din  : in std_logic_vector(7 downto 0) ;
       IRQ  : out std_logic;
       sout : out std_logic;
       dout : out std_logic_vector (7 downto 0) ;
       data_ready : out std_logic ;
       overrun_error : out std_logic;
       framing_error : out std_logic ;
       parity_error : out std_logic;
       IQR : out std_logic );
end yibu_control;


architecture behave of yibu_control is

component trans_port 
     port (rst,start_write,clk,ETBE : in std_logic ;
           din  : in std_logic_vector(7 downto 0) ;
           IRQ  : out std_logic;
           sout : out std_logic ) ;
end component;

component receiver
     port (rst,clk,rxd,ERBF : in std_logic ;
           dout : out std_logic_vector (7 downto 0) ;
           data_ready : out std_logic ;
           overrun_error : out std_logic;
           framing_error : out std_logic ;
           parity_error : out std_logic;
           IQR : out std_logic; 
           clk46: out std_logic) ;
end component;

signal tmp :std_logic;

begin

a1: trans_port port map(rst,start_write,clk,ETBE,din,IRQ,tmp);
a2: receiver port map(rst,clk,tmp,ERBF,dout,data_ready,overrun_error,framing_error,parity_error,IQR);

sout<=tmp;

end behave;