yibu_control.map.qmsg

分别完成了异步发送电路

{ "Info" "ISGN_MEGAFN_DESCENDANT" "receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node receiver:a2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:oflow_node\", which is child of megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 94 2 0 } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "receiver:a2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"receiver:a2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node receiver:a2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\", which is child of megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 199 5 0 } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "receiver:a2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"receiver:a2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|addcore:adder\[0\] receiver:a2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\|addcore:adder\|addcore:adder\[0\]\", which is child of megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\"" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 200 10 0 } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "receiver:a2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"receiver:a2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "receiver:a2\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs receiver:a2\|lpm_add_sub:Add1 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\|altshift:result_ext_latency_ffs\", which is child of megafunction instantiation \"receiver:a2\|lpm_add_sub:Add1\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 284 2 0 } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "receiver:a2\|lpm_add_sub:Add1 " "Info: Instantiated megafunction \"receiver:a2\|lpm_add_sub:Add1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 6 " "Info: Parameter \"LPM_WIDTH\" = \"6\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|yibu_control\|receiver:a2\|Rx_State 4 " "Info: State machine \"\|yibu_control\|receiver:a2\|Rx_State\" contains 4 states" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 32 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|yibu_control\|receiver:a2\|Rx_State " "Info: Selected Auto state machine encoding method for state machine \"\|yibu_control\|receiver:a2\|Rx_State\"" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 32 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|yibu_control\|receiver:a2\|Rx_State " "Info: Encoding result for state machine \"\|yibu_control\|receiver:a2\|Rx_State\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "2 " "Info: Completed encoding using 2 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "yibu_control\|receiver:a2\|Rx_State.state_bit_1 " "Info: Encoded state bit \"yibu_control\|receiver:a2\|Rx_State.state_bit_1\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "yibu_control\|receiver:a2\|Rx_State.state_bit_0 " "Info: Encoded state bit \"yibu_control\|receiver:a2\|Rx_State.state_bit_0\"" {  } {  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yibu_control\|receiver:a2\|Rx_State.s0 00 " "Info: State \"\|yibu_control\|receiver:a2\|Rx_State.s0\" uses code string \"00\"" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yibu_control\|receiver:a2\|Rx_State.s1 01 " "Info: State \"\|yibu_control\|receiver:a2\|Rx_State.s1\" uses code string \"01\"" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yibu_control\|receiver:a2\|Rx_State.s2 10 " "Info: State \"\|yibu_control\|receiver:a2\|Rx_State.s2\" uses code string \"10\"" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|yibu_control\|receiver:a2\|Rx_State.s3 11 " "Info: State \"\|yibu_control\|receiver:a2\|Rx_State.s3\" uses code string \"11\"" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 38 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 32 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "20 " "Info: Ignored 20 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "20 " "Info: Ignored 20 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "trans_port.vhd" "" { Text "D:/05606_王晓晨_18/sy2/trans_port.vhd" 17 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "146 " "Info: Implemented 146 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "13 " "Info: Implemented 13 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "118 " "Info: Implemented 118 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 12 09:04:12 2008 " "Info: Processing ended: Fri Sep 12 09:04:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}