yibu_control.map.qmsg

分别完成了异步发送电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 12 09:04:05 2008 " "Info: Processing started: Fri Sep 12 09:04:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off yibu_control -c yibu_control " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off yibu_control -c yibu_control" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "receiver.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file receiver.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 receiver-behave " "Info: Found design unit 1: receiver-behave" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 receiver " "Info: Found entity 1: receiver" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trans_port.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file trans_port.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 trans_port-behave " "Info: Found design unit 1: trans_port-behave" {  } { { "trans_port.vhd" "" { Text "D:/05606_王晓晨_18/sy2/trans_port.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 trans_port " "Info: Found entity 1: trans_port" {  } { { "trans_port.vhd" "" { Text "D:/05606_王晓晨_18/sy2/trans_port.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "yibu_control.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file yibu_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 yibu_control-behave " "Info: Found design unit 1: yibu_control-behave" {  } { { "yibu_control.vhd" "" { Text "D:/05606_王晓晨_18/sy2/yibu_control.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 yibu_control " "Info: Found entity 1: yibu_control" {  } { { "yibu_control.vhd" "" { Text "D:/05606_王晓晨_18/sy2/yibu_control.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "yibu_control " "Info: Elaborating entity \"yibu_control\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans_port trans_port:a1 " "Info: Elaborating entity \"trans_port\" for hierarchy \"trans_port:a1\"" {  } { { "yibu_control.vhd" "a1" { Text "D:/05606_王晓晨_18/sy2/yibu_control.vhd" 44 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "receiver receiver:a2 " "Info: Elaborating entity \"receiver\" for hierarchy \"receiver:a2\"" {  } { { "yibu_control.vhd" "a2" { Text "D:/05606_王晓晨_18/sy2/yibu_control.vhd" 45 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "LDSR receiver.vhd(22) " "Warning (10036): Verilog HDL or VHDL warning at receiver.vhd(22): object \"LDSR\" assigned a value but never read" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 22 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "rst receiver.vhd(121) " "Warning (10492): VHDL Process Statement warning at receiver.vhd(121): signal \"rst\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "receiver.vhd" "" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 121 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "receiver:a2\|cnt\[0\]~232 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"receiver:a2\|cnt\[0\]~232\"" {  } { { "receiver.vhd" "cnt\[0\]~232" { Text "D:/05606_王晓晨_18/sy2/receiver.vhd" 38 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "trans_port:a1\|tmp1\[0\]~248 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"trans_port:a1\|tmp1\[0\]~248\"" {  } { { "trans_port.vhd" "tmp1\[0\]~248" { Text "D:/05606_王晓晨_18/sy2/trans_port.vhd" 27 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "receiver:a2\|lpm_counter:cnt_rtl_0 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_counter:cnt_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "receiver:a2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add0\"" {  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "receiver:a2\|lpm_add_sub:Add0\|addcore:adder receiver:a2\|lpm_add_sub:Add0 " "Info: Elaborated megafunction instantiation \"receiver:a2\|lpm_add_sub:Add0\|addcore:adder\", which is child of megafunction instantiation \"receiver:a2\|lpm_add_sub:Add0\"" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 266 4 0 } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "receiver:a2\|lpm_add_sub:Add0 " "Info: Instantiated megafunction \"receiver:a2\|lpm_add_sub:Add0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 5 " "Info: Parameter \"LPM_WIDTH\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Info: Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ONE_INPUT_IS_CONSTANT YES " "Info: Parameter \"ONE_INPUT_IS_CONSTANT\" = \"YES\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 709 -1 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}