trans21.vhd

分别完成了异步发送电路

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(t_sig_o1_expected,t_sig_o2_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(o1,o2)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_o1_exp : o1_type := 'U';
VARIABLE last_o2_exp : o2_type := 'U';

VARIABLE on_first_change : trackvec := "11";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_expected_prev);
	write(txt,string'("| expected "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_prev);
	write(txt,string'("| real "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( t_sig_o1_expected_prev /= 'X' ) AND (t_sig_o1_expected_prev /= 'U' ) AND (t_sig_o1_prev /= t_sig_o1_expected_prev) AND (
	(t_sig_o1_expected_prev /= last_o1_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("IRQ",t_sig_o1_expected_prev,t_sig_o1_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_o1_exp := t_sig_o1_expected_prev;
END IF;
IF ( t_sig_o2_expected_prev /= 'X' ) AND (t_sig_o2_expected_prev /= 'U' ) AND (t_sig_o2_prev /= t_sig_o2_expected_prev) AND (
	(t_sig_o2_expected_prev /= last_o2_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("sout",t_sig_o2_expected_prev,t_sig_o2_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_o2_exp := t_sig_o2_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 300000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.trans_port_vhd_tb_types.ALL;                                         

ENTITY trans_port_vhd_vec_tst IS
END trans_port_vhd_vec_tst;
ARCHITECTURE trans_port_arch OF trans_port_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_clk : STD_LOGIC;
SIGNAL t_sig_din : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL t_sig_ETBE : STD_LOGIC;
SIGNAL t_sig_IRQ : STD_LOGIC;
SIGNAL t_sig_rst : STD_LOGIC;
SIGNAL t_sig_sout : STD_LOGIC;
SIGNAL t_sig_start_write : STD_LOGIC;
SIGNAL t_sig_sampler : sample_type;

COMPONENT trans_port
	PORT (
	clk : IN STD_LOGIC;
	din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	ETBE : IN STD_LOGIC;
	IRQ : OUT STD_LOGIC;
	rst : IN STD_LOGIC;
	sout : OUT STD_LOGIC;
	start_write : IN STD_LOGIC
	);
END COMPONENT;
COMPONENT trans_port_vhd_check_tst
PORT (
	o1 : IN o1_type;
	o2 : IN o2_type;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT trans_port_vhd_sample_tst
PORT (
	s1 : IN i1_type;
	s2 : IN i2_type;
	s3 : IN i3_type;
	s4 : IN i4_type;
	s5 : IN i5_type;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : trans_port
	PORT MAP (
-- list connections between master ports and signals
	clk => t_sig_clk,
	din => t_sig_din,
	ETBE => t_sig_ETBE,
	IRQ => t_sig_IRQ,
	rst => t_sig_rst,
	sout => t_sig_sout,
	start_write => t_sig_start_write
	);

-- clk
t_prcs_clk: PROCESS
BEGIN
LOOP
	t_sig_clk <= '0';
	WAIT FOR 200000 ps;
	t_sig_clk <= '1';
	WAIT FOR 200000 ps;
	IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_clk;

-- rst
t_prcs_rst: PROCESS
BEGIN
	t_sig_rst <= '0';
	WAIT FOR 800000 ps;
	t_sig_rst <= '1';
	WAIT FOR 800000 ps;
	t_sig_rst <= '0';
WAIT;
END PROCESS t_prcs_rst;

-- start_write
t_prcs_start_write: PROCESS
BEGIN
	t_sig_start_write <= '0';
	WAIT FOR 2000000 ps;
	t_sig_start_write <= '1';
	WAIT FOR 1200000 ps;
	t_sig_start_write <= '0';
WAIT;
END PROCESS t_prcs_start_write;
-- din[7]
t_prcs_din_7: PROCESS
BEGIN
	t_sig_din(7) <= '1';
WAIT;
END PROCESS t_prcs_din_7;
-- din[6]
t_prcs_din_6: PROCESS
BEGIN
	t_sig_din(6) <= '0';
WAIT;
END PROCESS t_prcs_din_6;
-- din[5]
t_prcs_din_5: PROCESS
BEGIN
	t_sig_din(5) <= '0';
WAIT;
END PROCESS t_prcs_din_5;
-- din[4]
t_prcs_din_4: PROCESS
BEGIN
	t_sig_din(4) <= '1';
WAIT;
END PROCESS t_prcs_din_4;
-- din[3]
t_prcs_din_3: PROCESS
BEGIN
	t_sig_din(3) <= '0';
WAIT;
END PROCESS t_prcs_din_3;
-- din[2]
t_prcs_din_2: PROCESS
BEGIN
	t_sig_din(2) <= '0';
WAIT;
END PROCESS t_prcs_din_2;
-- din[1]
t_prcs_din_1: PROCESS
BEGIN
	t_sig_din(1) <= '1';
WAIT;
END PROCESS t_prcs_din_1;
-- din[0]
t_prcs_din_0: PROCESS
BEGIN
	t_sig_din(0) <= '0';
WAIT;
END PROCESS t_prcs_din_0;

-- ETBE
t_prcs_ETBE: PROCESS
BEGIN
	t_sig_ETBE <= '0';
	WAIT FOR 121600000 ps;
	t_sig_ETBE <= '1';
	WAIT FOR 9600000 ps;
	t_sig_ETBE <= '0';
WAIT;
END PROCESS t_prcs_ETBE;
tb_sample : trans_port_vhd_sample_tst
PORT MAP (
	s1 => t_sig_clk,
	s2 => t_sig_din,
	s3 => t_sig_ETBE,
	s4 => t_sig_rst,
	s5 => t_sig_start_write,
	sampler => t_sig_sampler
	);

tb_out : trans_port_vhd_check_tst
PORT MAP (
	o1 => t_sig_IRQ,
	o2 => t_sig_sout,
	sampler => t_sig_sampler
	);
END trans_port_arch;