📄 yibu_control.fit.rpt
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; receiver:a2|count[2] ; 5 ;
; receiver:a2|lpm_counter:cnt_rtl_0|dffs[0] ; 4 ;
; trans_port:a1|temp[1] ; 4 ;
; trans_port:a1|temp[2] ; 4 ;
; trans_port:a1|temp[3] ; 4 ;
; trans_port:a1|temp[4] ; 4 ;
; trans_port:a1|temp[5] ; 4 ;
; trans_port:a1|temp[6] ; 4 ;
; trans_port:a1|temp[7] ; 4 ;
+-----------------------------------------------+---------+
+-------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+--------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+--------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 161 / 288 ( 56 % ) ;
; PIAs ; 174 / 288 ( 60 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 21.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 1 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 3 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 2 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 14.75) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 7 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 17 ;
+--------------------------+------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC12 ; clk, receiver:a2|shift[4], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[5], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[5], receiver:a2|shift[6], receiver:a2|process0~41, receiver:a2|rsr[4], receiver:a2|shift[5]~565 ;
; A ; LC10 ; clk, yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|count[0], receiver:a2|count[1], rst ; receiver:a2|count[1], receiver:a2|count[2], receiver:a2|count[3], receiver:a2|count[4], yibu_control|receiver:a2|Rx_State.state_bit_1, yibu_control|receiver:a2|Rx_State.state_bit_0 ;
; A ; LC9 ; receiver:a2|shift[3], receiver:a2|shift[2], receiver:a2|shift[4], receiver:a2|shift[1] ; receiver:a2|LDRB, receiver:a2|PE, receiver:a2|rsr[0], receiver:a2|rsr[1], receiver:a2|rsr[2], receiver:a2|rsr[3], receiver:a2|rsr[4], receiver:a2|rsr[5], receiver:a2|rsr[6], receiver:a2|rsr[7], receiver:a2|shift[8]~550, receiver:a2|shift[7]~555, receiver:a2|shift[6]~560, receiver:a2|shift[5]~565, receiver:a2|shift[4]~570, receiver:a2|shift[3]~575, receiver:a2|shift[2]~580 ;
; A ; LC13 ; clk, yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|count[0], receiver:a2|count[1], receiver:a2|count[2], rst ; receiver:a2|count[2], receiver:a2|count[3], receiver:a2|count[4], yibu_control|receiver:a2|Rx_State.state_bit_1, yibu_control|receiver:a2|Rx_State.state_bit_0 ;
; A ; LC15 ; clk, receiver:a2|shift[3], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[4], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[4], receiver:a2|process0~34, receiver:a2|shift[5], receiver:a2|rsr[5], receiver:a2|shift[4]~570 ;
; A ; LC8 ; clk, yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|count[2], receiver:a2|count[0], receiver:a2|count[1], receiver:a2|count[3], rst ; receiver:a2|count[3], receiver:a2|count[4], yibu_control|receiver:a2|Rx_State.state_bit_1, yibu_control|receiver:a2|Rx_State.state_bit_0 ;
; A ; LC6 ; clk, receiver:a2|shift[0], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[1], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[1], receiver:a2|shift[2], receiver:a2|process0~34 ;
; A ; LC14 ; clk, yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|count[3], receiver:a2|count[2], receiver:a2|count[0], receiver:a2|count[1], receiver:a2|count[4], rst ; receiver:a2|count[4], yibu_control|receiver:a2|Rx_State.state_bit_1, yibu_control|receiver:a2|Rx_State.state_bit_0 ;
; A ; LC16 ; clk, receiver:a2|shift[2], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[3], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[3], receiver:a2|shift[4], receiver:a2|process0~34, receiver:a2|rsr[6], receiver:a2|shift[3]~575 ;
; A ; LC4 ; clk, receiver:a2|shift[1], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[2], receiver:a2|shift[3], receiver:a2|process0~34, receiver:a2|rsr[7], receiver:a2|shift[2]~580 ;
; A ; LC2 ; clk, receiver:a2|shift[7], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[8], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[8], receiver:a2|process0~41, receiver:a2|shift[9], receiver:a2|rsr[1], receiver:a2|shift[8]~550 ;
; A ; LC3 ; clk, trans_port:a1|sout, rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[0], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[0], receiver:a2|FE, receiver:a2|shift[1], receiver:a2|LDRB, receiver:a2|PE, receiver:a2|rsr[0], receiver:a2|rsr[1], receiver:a2|rsr[2], receiver:a2|rsr[3], receiver:a2|rsr[4], receiver:a2|rsr[5], receiver:a2|rsr[6], receiver:a2|rsr[7], receiver:a2|shift[8]~550, receiver:a2|shift[7]~555, receiver:a2|shift[6]~560, receiver:a2|shift[5]~565, receiver:a2|shift[4]~570, receiver:a2|shift[3]~575, receiver:a2|shift[2]~580 ;
; A ; LC11 ; clk, receiver:a2|shift[6], rst, receiver:a2|lpm_counter:cnt_rtl_0|dffs[3], yibu_control|receiver:a2|Rx_State.state_bit_0, yibu_control|receiver:a2|Rx_State.state_bit_1, receiver:a2|clkdiv[0], receiver:a2|clkdiv[1], receiver:a2|clkdiv[2], receiver:a2|clkdiv[3], receiver:a2|clkdiv[4], receiver:a2|clkdiv[5], receiver:a2|shift[7], receiver:a2|lpm_counter:cnt_rtl_0|dffs[2], receiver:a2|lpm_counter:cnt_rtl_0|dffs[1] ; receiver:a2|shift[7], receiver:a2|shift[8], receiver:a2|process0~41, receiver:a2|rsr[2], receiver:a2|shift[7]~555 ⌨️ 快捷键说明
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