division.vhd

来自「分别用分频比交错法及累加器分频法完成非整数分频器设计。」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity division is port
(F_in: in std_logic; 
 reset:in std_logic;  
 F_out1: out std_logic;
 F_out2:out std_logic);
end division;
architecture behave of division is
component div89
    port(F_IN:in std_logic;
         reset:in std_logic;
         F_out1:out std_logic);
  end component;

component accumulater     
	port(F_IN: in std_logic;
		 reset:in std_logic;
		 F_OUT2: out std_logic);
	end component;
 
begin
a:div89 port map(F_in,reset,F_out1);
b:accumulater port map(F_in,reset,F_OUT2);
end;