📄 myclock.hif

📁 用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选
💻 HIF
字号:
Version 4.1 Build 181 06/29/2004 SJ Full Version
28
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# entity
lpm_add_sub
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|lpm_add_sub.tdf
1088009426
6
# storage
db|myclock.(5).cnf
db|myclock.(5).cnf
# user_parameter {
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
YES
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
9
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_rnh
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
cin
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
result0
result1
result2
result3
result4
result5
result6
result7
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|addcore.inc
1081476628
c:|altera|quartus41|libraries|megafunctions|look_add.inc
1081478428
c:|altera|quartus41|libraries|megafunctions|bypassff.inc
1081477994
c:|altera|quartus41|libraries|megafunctions|altshift.inc
1081477602
c:|altera|quartus41|libraries|megafunctions|alt_stratix_add_sub.inc
1081476992
c:|altera|quartus41|libraries|megafunctions|alt_mercury_add_sub.inc
1081476976
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
addcore
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|addcore.tdf
1088009426
6
# storage
db|myclock.(6).cnf
db|myclock.(6).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
8
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
datab0
datab1
datab2
datab3
datab4
datab5
datab6
datab7
cin
result0
result1
result2
result3
result4
result5
result6
result7
bg_out
bp_out
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|addcore.inc
1081476628
c:|altera|quartus41|libraries|megafunctions|a_csnbuffer.inc
1081476420
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|a_csnbuffer.tdf
1088009426
6
# storage
db|myclock.(7).cnf
db|myclock.(7).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sout0
}
# end
# entity
a_csnbuffer
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|a_csnbuffer.tdf
1088009426
6
# storage
db|myclock.(8).cnf
db|myclock.(8).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sin0
sin1
sin2
sin3
sin4
sin5
sin6
sin7
sout0
sout1
sout2
sout3
sout4
sout5
sout6
sout7
}
# end
# entity
look_add
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|look_add.tdf
1088009426
6
# storage
db|myclock.(9).cnf
db|myclock.(9).cnf
# user_parameter {
width
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
bg_in0
bp_in0
cin
cout0
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|look_add.inc
1081478428
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
altshift
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altshift.tdf
1088009432
6
# storage
db|myclock.(10).cnf
db|myclock.(10).cnf
# user_parameter {
WIDTH
8
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
result0
result1
result2
result3
result4
result5
result6
result7
}
# end
# entity
altshift
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altshift.tdf
1088009432
6
# storage
db|myclock.(11).cnf
db|myclock.(11).cnf
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
result0
}
# end
# entity
lpm_add_sub
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|lpm_add_sub.tdf
1088009426
6
# storage
db|myclock.(12).cnf
db|myclock.(12).cnf
# user_parameter {
LPM_WIDTH
11
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
YES
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
9
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_5ph
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
cin
dataa0
dataa10
dataa1
dataa2
dataa3
dataa4
dataa5
dataa6
dataa7
dataa8
dataa9
datab0
datab10
datab1
datab2
datab3
datab4
datab5
datab6
datab7
datab8
datab9
result0
result10
result1
result2
result3
result4
result5
result6
result7
result8
result9
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|addcore.inc
1081476628
c:|altera|quartus41|libraries|megafunctions|look_add.inc
1081478428
c:|altera|quartus41|libraries|megafunctions|bypassff.inc
1081477994
c:|altera|quartus41|libraries|megafunctions|altshift.inc
1081477602
c:|altera|quartus41|libraries|megafunctions|alt_stratix_add_sub.inc
1081476992
c:|altera|quartus41|libraries|megafunctions|alt_mercury_add_sub.inc
1081476976
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
addcore
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|addcore.tdf
1088009426
6
# storage
db|myclock.(13).cnf
db|myclock.(13).cnf
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
8
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
DEFAULT
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
}
# used_port {
dataa0
dataa1
dataa2
datab0
datab1
datab2
cin
result0
result1
result2
bg_out
bp_out
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|addcore.inc
1081476628
c:|altera|quartus41|libraries|megafunctions|a_csnbuffer.inc
1081476420
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
look_add
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|look_add.tdf
1088009426
6
# storage
db|myclock.(14).cnf
db|myclock.(14).cnf
# user_parameter {
width
2
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
MAX7000S
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
bg_in0
bg_in1
bp_in0
bp_in1
cin
cout0
cout1
}
# include_file {
c:|altera|quartus41|libraries|megafunctions|look_add.inc
1081478428
c:|altera|quartus41|libraries|megafunctions|aglobal41.inc
1088009406
}
# end
# entity
altshift
# case_insensitive
# source_file
c:|altera|quartus41|libraries|megafunctions|altshift.tdf
1088009432
6
# storage
db|myclock.(15).cnf
db|myclock.(15).cnf
# user_parameter {
WIDTH
11
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
}
# end
# entity
myclock
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
myclock.vhd
1197533536
4
# storage
db|myclock.(0).cnf
db|myclock.(0).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
distribute_frq
# architecture
A:arch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
distribute_frq.vhd
1197533650
4
# storage
db|myclock.(1).cnf
db|myclock.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
time_form
# architecture
A:arch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
time_form.vhd
1197533668
4
# storage
db|myclock.(3).cnf
db|myclock.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
display
# architecture
A:arch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
display.vhd
1197533630
4
# storage
db|myclock.(4).cnf
db|myclock.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
clk_and_modify
# architecture
A:arch
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
clk_and_modify.vhd
1160283810
4
# storage
db|myclock.(2).cnf
db|myclock.(2).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# complete
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