myclock.hier_info

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

|myclock
clk => time_form:u3.clk
clk => distribute_frq:u1.clk
reset => clk_and_modify:u2.reset
choose => clk_and_modify:u2.choose
modify_min_hour => clk_and_modify:u2.modify_min_hour
div_choose_state => clk_and_modify:u2.div_choose_state
revert => time_form:u3.revert
alarm_modify => clk_and_modify:u2.alarm_modify
alarm <= clk_and_modify:u2.alarm
sel[0] <= display:u4.sel[0]
sel[1] <= display:u4.sel[1]
sel[2] <= display:u4.sel[2]
sel[3] <= display:u4.sel[3]
sel[4] <= display:u4.sel[4]
sel[5] <= display:u4.sel[5]
am_or_pm <= time_form:u3.am_or_pm
mux_o[0] <= display:u4.mux_o[0]
mux_o[1] <= display:u4.mux_o[1]
mux_o[2] <= display:u4.mux_o[2]
mux_o[3] <= display:u4.mux_o[3]
mux_o[4] <= display:u4.mux_o[4]
mux_o[5] <= display:u4.mux_o[5]
mux_o[6] <= display:u4.mux_o[6]
mux_o[7] <= mux_o~2.DB_MAX_OUTPUT_PORT_TYPE


|myclock|distribute_frq:u1
clk => q1[9].CLK
clk => q1[8].CLK
clk => q1[7].CLK
clk => q1[6].CLK
clk => q1[5].CLK
clk => q1[4].CLK
clk => q1[3].CLK
clk => q1[2].CLK
clk => q1[1].CLK
clk => q1[0].CLK
clk => y.CLK
clk => q1[10].CLK
clk400h <= y.DB_MAX_OUTPUT_PORT_TYPE
clk1Mh <= y2.DB_MAX_OUTPUT_PORT_TYPE


|myclock|clk_and_modify:u2
clk1Mh => sec_l[2].CLK
clk1Mh => sec_l[1].CLK
clk1Mh => sec_l[0].CLK
clk1Mh => sec_h[2].CLK
clk1Mh => sec_h[1].CLK
clk1Mh => sec_h[0].CLK
clk1Mh => min_l[3].CLK
clk1Mh => min_l[2].CLK
clk1Mh => min_l[1].CLK
clk1Mh => min_l[0].CLK
clk1Mh => min_h[2].CLK
clk1Mh => min_h[1].CLK
clk1Mh => min_h[0].CLK
clk1Mh => hour_l[3].CLK
clk1Mh => hour_l[2].CLK
clk1Mh => hour_l[1].CLK
clk1Mh => hour_l[0].CLK
clk1Mh => hour_h[1].CLK
clk1Mh => hour_h[0].CLK
clk1Mh => sec_one[3]~reg0.CLK
clk1Mh => sec_one[2]~reg0.CLK
clk1Mh => sec_one[1]~reg0.CLK
clk1Mh => sec_one[0]~reg0.CLK
clk1Mh => sec_ten[2]~reg0.CLK
clk1Mh => sec_ten[1]~reg0.CLK
clk1Mh => sec_ten[0]~reg0.CLK
clk1Mh => min_one[3]~reg0.CLK
clk1Mh => min_one[2]~reg0.CLK
clk1Mh => min_one[1]~reg0.CLK
clk1Mh => min_one[0]~reg0.CLK
clk1Mh => min_ten[2]~reg0.CLK
clk1Mh => min_ten[1]~reg0.CLK
clk1Mh => min_ten[0]~reg0.CLK
clk1Mh => hour_one[3]~reg0.CLK
clk1Mh => hour_one[2]~reg0.CLK
clk1Mh => hour_one[1]~reg0.CLK
clk1Mh => hour_one[0]~reg0.CLK
clk1Mh => hour_ten[1]~reg0.CLK
clk1Mh => hour_ten[0]~reg0.CLK
clk1Mh => min_l_alarm[3].CLK
clk1Mh => min_l_alarm[2].CLK
clk1Mh => min_l_alarm[1].CLK
clk1Mh => min_l_alarm[0].CLK
clk1Mh => min_h_alarm[2].CLK
clk1Mh => min_h_alarm[1].CLK
clk1Mh => min_h_alarm[0].CLK
clk1Mh => hour_l_alarm[3].CLK
clk1Mh => hour_l_alarm[2].CLK
clk1Mh => hour_l_alarm[1].CLK
clk1Mh => hour_l_alarm[0].CLK
clk1Mh => hour_h_alarm[1].CLK
clk1Mh => hour_h_alarm[0].CLK
clk1Mh => sec_l[3].CLK
reset => sec_l[2].ACLR
reset => sec_l[1].ACLR
reset => sec_l[0].ACLR
reset => sec_h[2].ACLR
reset => sec_h[1].ACLR
reset => sec_h[0].ACLR
reset => min_l[3].ACLR
reset => min_l[2].ACLR
reset => min_l[1].ACLR
reset => min_l[0].ACLR
reset => min_h[2].ACLR
reset => min_h[1].ACLR
reset => min_h[0].ACLR
reset => hour_l[3].ACLR
reset => hour_l[2].ACLR
reset => hour_l[1].ACLR
reset => hour_l[0].ACLR
reset => hour_h[1].ACLR
reset => hour_h[0].ACLR
reset => sec_one~4.OUTPUTSELECT
reset => sec_one~5.OUTPUTSELECT
reset => sec_one~6.OUTPUTSELECT
reset => sec_one~7.OUTPUTSELECT
reset => sec_ten~3.OUTPUTSELECT
reset => sec_ten~4.OUTPUTSELECT
reset => sec_ten~5.OUTPUTSELECT
reset => min_one~4.OUTPUTSELECT
reset => min_one~5.OUTPUTSELECT
reset => min_one~6.OUTPUTSELECT
reset => min_one~7.OUTPUTSELECT
reset => min_ten~3.OUTPUTSELECT
reset => min_ten~4.OUTPUTSELECT
reset => min_ten~5.OUTPUTSELECT
reset => hour_one~4.OUTPUTSELECT
reset => hour_one~5.OUTPUTSELECT
reset => hour_one~6.OUTPUTSELECT
reset => hour_one~7.OUTPUTSELECT
reset => hour_ten~2.OUTPUTSELECT
reset => hour_ten~3.OUTPUTSELECT
reset => min_l_alarm~24.OUTPUTSELECT
reset => min_l_alarm~25.OUTPUTSELECT
reset => min_l_alarm~26.OUTPUTSELECT
reset => min_l_alarm~27.OUTPUTSELECT
reset => min_h_alarm~18.OUTPUTSELECT
reset => min_h_alarm~19.OUTPUTSELECT
reset => min_h_alarm~20.OUTPUTSELECT
reset => hour_l_alarm~28.OUTPUTSELECT
reset => hour_l_alarm~29.OUTPUTSELECT
reset => hour_l_alarm~30.OUTPUTSELECT
reset => hour_l_alarm~31.OUTPUTSELECT
reset => hour_h_alarm~12.OUTPUTSELECT
reset => hour_h_alarm~13.OUTPUTSELECT
reset => sec_l[3].ACLR
choose => p1~38.IN0
modify_min_hour => min_l~31.OUTPUTSELECT
modify_min_hour => min_l~32.OUTPUTSELECT
modify_min_hour => min_l~33.OUTPUTSELECT
modify_min_hour => min_l~34.OUTPUTSELECT
modify_min_hour => min_h~21.OUTPUTSELECT
modify_min_hour => min_h~22.OUTPUTSELECT
modify_min_hour => min_h~23.OUTPUTSELECT
modify_min_hour => hour_l~44.OUTPUTSELECT
modify_min_hour => hour_l~45.OUTPUTSELECT
modify_min_hour => hour_l~46.OUTPUTSELECT
modify_min_hour => hour_l~47.OUTPUTSELECT
modify_min_hour => hour_h~20.OUTPUTSELECT
modify_min_hour => hour_h~21.OUTPUTSELECT
modify_min_hour => min_l_alarm~16.OUTPUTSELECT
modify_min_hour => min_l_alarm~17.OUTPUTSELECT
modify_min_hour => min_l_alarm~18.OUTPUTSELECT
modify_min_hour => min_l_alarm~19.OUTPUTSELECT
modify_min_hour => min_h_alarm~12.OUTPUTSELECT
modify_min_hour => min_h_alarm~13.OUTPUTSELECT
modify_min_hour => min_h_alarm~14.OUTPUTSELECT
modify_min_hour => hour_l_alarm~20.OUTPUTSELECT
modify_min_hour => hour_l_alarm~21.OUTPUTSELECT
modify_min_hour => hour_l_alarm~22.OUTPUTSELECT
modify_min_hour => hour_l_alarm~23.OUTPUTSELECT
modify_min_hour => hour_h_alarm~8.OUTPUTSELECT
modify_min_hour => hour_h_alarm~9.OUTPUTSELECT
div_choose_state => choose_state.CLK
alarm <= p1~87.DB_MAX_OUTPUT_PORT_TYPE
sec_one[0] <= sec_one[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_one[1] <= sec_one[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_one[2] <= sec_one[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_one[3] <= sec_one[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_ten[0] <= sec_ten[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_ten[1] <= sec_ten[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec_ten[2] <= sec_ten[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_one[0] <= min_one[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_one[1] <= min_one[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_one[2] <= min_one[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_one[3] <= min_one[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_ten[0] <= min_ten[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_ten[1] <= min_ten[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
min_ten[2] <= min_ten[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_one[0] <= hour_one[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_one[1] <= hour_one[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_one[2] <= hour_one[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_one[3] <= hour_one[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_ten[0] <= hour_ten[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_ten[1] <= hour_ten[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
alarm_modify => p1~19.IN0
ch_state <= choose_state.DB_MAX_OUTPUT_PORT_TYPE


|myclock|time_form:u3
clk => hour_h_12[0]~reg0.CLK
clk => hour_l_12[3]~reg0.CLK
clk => hour_l_12[2]~reg0.CLK
clk => hour_l_12[1]~reg0.CLK
clk => hour_l_12[0]~reg0.CLK
clk => am_or_pm~reg0.CLK
clk => hour_h_12[1]~reg0.CLK
revert => state.CLK
hour_l_24[0] => LessThan~0.IN8
hour_l_24[0] => hour_l_12[0]~reg0.DATAIN
hour_l_24[1] => LessThan~0.IN7
hour_l_24[1] => add~2.IN6
hour_l_24[1] => hour_l_12~3.DATAA
hour_l_24[1] => hour_l_12~6.DATAB
hour_l_24[1] => hour_l_12~9.DATAA
hour_l_24[2] => LessThan~0.IN6
hour_l_24[2] => add~2.IN5
hour_l_24[2] => hour_l_12~2.DATAA
hour_l_24[2] => hour_l_12~5.DATAB
hour_l_24[2] => hour_l_12~8.DATAA
hour_l_24[3] => LessThan~0.IN5
hour_l_24[3] => add~0.IN2
hour_l_24[3] => hour_l_12~0.DATAB
hour_l_24[3] => add~2.IN4
hour_l_24[3] => hour_l_12~1.DATAA
hour_l_24[3] => hour_l_12~7.DATAA
hour_h_24[0] => LessThan~1.IN4
hour_h_24[0] => hour_h_12~1.DATAB
hour_h_24[0] => LessThan~2.IN4
hour_h_24[0] => add~1.IN4
hour_h_24[0] => hour_h_12~3.DATAA
hour_h_24[0] => hour_h_12~7.DATAA
hour_h_24[1] => LessThan~1.IN3
hour_h_24[1] => hour_h_12~0.DATAB
hour_h_24[1] => LessThan~2.IN3
hour_h_24[1] => add~1.IN3
hour_h_24[1] => hour_h_12~2.DATAA
hour_h_24[1] => hour_h_12~6.DATAA
hour_l_12[0] <= hour_l_12[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_l_12[1] <= hour_l_12[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_l_12[2] <= hour_l_12[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_l_12[3] <= hour_l_12[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_h_12[0] <= hour_h_12[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
hour_h_12[1] <= hour_h_12[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
am_or_pm <= am_or_pm~reg0.DB_MAX_OUTPUT_PORT_TYPE


|myclock|display:u4
clk400h => q[1].CLK
clk400h => q[0].CLK
clk400h => mux_out[3].CLK
clk400h => mux_out[2].CLK
clk400h => mux_out[1].CLK
clk400h => mux_out[0].CLK
clk400h => sel[5]~reg0.CLK
clk400h => sel[4]~reg0.CLK
clk400h => sel[3]~reg0.CLK
clk400h => sel[2]~reg0.CLK
clk400h => sel[1]~reg0.CLK
clk400h => sel[0]~reg0.CLK
clk400h => q[2].CLK
a[0] => Mux~3.IN2
a[1] => Mux~2.IN2
a[2] => Mux~1.IN3
a[3] => Mux~0.IN5
b[0] => Mux~3.IN3
b[1] => Mux~2.IN3
b[2] => Mux~1.IN4
c[0] => Mux~3.IN4
c[1] => Mux~2.IN4
c[2] => Mux~1.IN5
c[3] => Mux~0.IN6
d[0] => Mux~3.IN5
d[1] => Mux~2.IN5
d[2] => Mux~1.IN6
e[0] => Mux~3.IN6
e[1] => Mux~2.IN6
e[2] => Mux~1.IN7
e[3] => Mux~0.IN7
f[0] => Mux~3.IN7
f[1] => Mux~2.IN7
mux_o[0] <= Mux~16.DB_MAX_OUTPUT_PORT_TYPE
mux_o[1] <= Mux~15.DB_MAX_OUTPUT_PORT_TYPE
mux_o[2] <= Mux~14.DB_MAX_OUTPUT_PORT_TYPE
mux_o[3] <= Mux~13.DB_MAX_OUTPUT_PORT_TYPE
mux_o[4] <= Mux~12.DB_MAX_OUTPUT_PORT_TYPE
mux_o[5] <= Mux~11.DB_MAX_OUTPUT_PORT_TYPE
mux_o[6] <= Mux~10.DB_MAX_OUTPUT_PORT_TYPE
mux_o[7] <= <GND>
sel[0] <= sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[3] <= sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[4] <= sel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sel[5] <= sel[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE