myclock.vhd

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity myclock is
port(clk,reset,choose,modify_min_hour,div_choose_state,revert,alarm_modify:in std_logic;
     alarm:out std_logic;
     sel:out std_logic_vector(5 downto 0);         --数码管选通信号
     am_or_pm:out std_logic;
     mux_o: out std_logic_vector(7 downto 0));     --数码管显示信号
end;

architecture arch of myclock is
signal clk400_signal,clk1M_signal,choose_state_signal:std_logic;
signal sec_one_signal,min_one_signal,hour_one_signal,hour_l_12_signal:integer range 0 to 9;
signal sec_ten_signal,min_ten_signal:integer range 0 to 5;
signal hour_ten_signal:integer range 0 to 2;
signal hour_h_12_signal:integer range 0 to 2;
signal mux_o_signal:std_logic_vector(7 downto 0);
signal sel_signal:std_logic_vector(5 downto 0);


component distribute_frq        --分频模块
   port(clk: in  std_logic;
        clk400h: out std_logic;        
        clk1Mh: out std_logic
        );
end component;

component clk_and_modify        --时钟跳动，修改，闹钟模块
    port(clk1Mh:in std_logic; 
         reset:in std_logic;     
         choose:in std_logic;  
         modify_min_hour,div_choose_state:in std_logic;  
         alarm:out std_logic;       
         sec_one:out integer range 0 to 9; 
         sec_ten:out integer range 0 to 5;
         min_one:out integer range 0 to 9; 
         min_ten:out integer range 0 to 5;
         hour_one:out integer range 0 to 9;     
         hour_ten:out integer range 0 to 2;
         alarm_modify:in std_logic;
         ch_state:out std_logic
         );
end component;

component time_form           --时制模块
    port(clk,revert:in std_logic;
         hour_l_24:in integer range 0 to 9;
         hour_h_24:in integer range 0 to 2;
         hour_l_12:out integer range 0 to 9;
         hour_h_12:out integer range 0 to 2;
         am_or_pm:out std_logic
         );
end component;

component display            --显示模块
    port (clk400h: in std_logic;
          a:in integer range 0 to 9;
          b:in integer range 0 to 5;
          c:in integer range 0 to 9;
          d:in integer range 0 to 5;
          e:in integer range 0 to 9;
          f:in integer range 0 to 2;
          mux_o :out std_logic_vector(7 downto 0);--数码管显示数组
          sel :out std_logic_vector(5 downto 0)   --数码管选通数组
          --choose_state:in std_logic
          );  
end component;

begin  

u1:distribute_frq port map(clk,clk400_signal,  --获得分频信号
                           clk1M_signal);

u2:clk_and_modify port map(clk1M_signal,reset,   --时钟走动，修改后传到时制模块             
                           choose,
                           modify_min_hour,
                           div_choose_state,
                           alarm,
                           sec_one_signal,sec_ten_signal,
                           min_one_signal,min_ten_signal,
                           hour_one_signal,hour_ten_signal,
                           
                           alarm_modify,choose_state_signal);

u3:time_form port map(clk,                      --接受时间信号，根据选择时制进行显示
                      revert,                  
                      hour_one_signal,hour_ten_signal,
                      hour_l_12_signal,hour_h_12_signal,
                      am_or_pm);



u4:display port map(clk400_signal,              --显示
                    sec_one_signal,
                    sec_ten_signal,
                    min_one_signal,
                    min_ten_signal,
                    hour_l_12_signal,
                    hour_h_12_signal,
               
                    mux_o_signal,
                    sel_signal);



p1:process(clk)
begin

case choose_state_signal is
    when '1' => if sel_signal="111011" then
                   mux_o<=(mux_o_signal or "10000000");
                else mux_o<=mux_o_signal;
                end if;
    when '0' => if sel_signal="101111" then
                   mux_o<=(mux_o_signal or "10000000");
                else mux_o<=mux_o_signal;
                end if;
    when others=> null;
end case;
end process;

sel<=sel_signal;
end;