myclock.map.summary

来自「用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小」· SUMMARY 代码 · 共 10 行

Flow Status : Successful - Sun Dec 30 17:07:22 2007
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : myclock
Top-level Entity Name : myclock
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Production
Total macrocells : 128
Total pins : 23