time_form.vhd

用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;

entity time_form is
port(clk,revert:in std_logic;
     hour_l_24:in integer range 0 to 9;
     hour_h_24:in integer range 0 to 2;
     hour_l_12:out integer range 0 to 9;
     hour_h_12:out integer range 0 to 2;
     am_or_pm:out std_logic
     );
end;

architecture arch of time_form is
signal state:std_logic;  
begin
p1:process(clk)
   begin
      if rising_edge (clk)then
         if  state ='1' then  
            if (hour_l_24 <2)then     --判断0，1，10，11，20，21
               if hour_h_24<2 then
                   hour_h_12<=hour_h_24;hour_l_12<=hour_l_24; am_or_pm<='0';
               else hour_h_12<=0;hour_l_12<=hour_l_24+8;am_or_pm<='1';
               end if;
            elsif hour_h_24>0 then    --判断除上面数外的其他数
               hour_h_12<=hour_h_24-1;hour_l_12<=hour_l_24-2;am_or_pm<='1';        
            else hour_h_12<=hour_h_24;hour_l_12<=hour_l_24; am_or_pm<='0';
            end if;               
         else  hour_h_12<=hour_h_24;hour_l_12<=hour_l_24; am_or_pm<='0';
         end if;
      end if;
end process;
p2:process(revert)       --按一次revert键state 就变一次来选择时制
   begin
     if (revert'event and revert='1')then
        state<=not state;
     end if;
end process;
end;