i2c_master_tb.v

Verilog for I2C core source code

/*********************************************************************
File name: 		  i2c_master_tb.v
Module name:	          i2c_master_tb	
Author:		         atuhappy( 陈亮)
Email：                  [e-mail]    
Version:			1.0
Date:				2004.7.27


Function Description:
测试I2C Master Core
						
*********************************************************************/
`include "../src/params.v"
module i2c_master_tb ;

reg clk, rst_n, cs;
reg [2 : 0] addr;
reg wr, rd;
reg [7 : 0] host_din;
wire [7 : 0] host_dout;

wire scl;
wire sda_o, sda_oe;
reg sda_i;
wire int;


i2c_master    top(.CLK         ( clk         ),
                  .RST_N       ( rst_n       ),
                  .CS          ( cs          ),
                  .ADDR        ( addr        ),
                  .WR          ( wr          ),
                  .RD          ( rd          ),
                  .HOST_DIN    ( host_din    ),
                  .HOST_DOUT   ( host_dout   ),
                  .INT         ( int         ), 
                  .SCL         ( scl         ),
                  .SDA_I       ( sda_i       ),
                  .SDA_O       ( sda_o       ),
                  .SDA_OE      ( sda_oe      ));
                  
initial begin
       clk = 1; 
       rst_n = 0;
       cs = 0;
       addr = 0;
       wr = 0;
       rd = 0;
       host_din = 0;
       sda_i = 0;
#10    rst_n = 1;
       cs = 1;       
#10    write   (0, 8'b0100_1010);   //器件地址
       write   (1, 8'b0101_0101);   //目标寄存器地址
       write   (2, 8'b0000_0010);   //输出数据个数  2个   
       write   (3, 8'b1010_1010);   //输出数据
       write   (5, 8'b0000_0011);   //方向为写，并启动
       
#100   read    (5);
       @(posedge int);           //第一个数据已锁存
       write   (3, 8'b1010_1010);   //输出第2个数据
                  
       @(posedge int);          //第2个数据已锁存  
       #10
       read    (4);
#1000  write   (5, 8'b0000_0001);   //方向为读，并启动    
       sda_i = 1;  
       @(posedge int)              //读回第一个数据
       read (3);
       @(posedge int)             //读回第2个数据
       read (3);        
       
#1000  $stop;  
       $finish;        

end    

always
 #5 clk = ~clk;              


task write;
  input [2 : 0] a;
  input [7 : 0] d;
  begin
    addr = a;
    host_din = d;
    #10 wr = 1;
    #10 wr = 0;
  end
endtask 

task read;
  input [2 : 0] a;
  begin
    addr = a;
    #10 rd = 1;
    #10 rd = 0;
  end
endtask                    

endmodule