bit_ctrl.v

Verilog for I2C core source code

/*********************************************************************
File name: 		  bit_ctrl.v
Module name:	          bit_ctrl	
Author:		         atuhappy( 陈亮)
Email：                  [e-mail]    
Version:			1.0
Date:				2004.7.23


Function Description:
产生I2C的SCL、SDA
						
*********************************************************************/

//start:
//      SCL	~~~~~~~~~~\____
//	SDA	~~~~~~~~\______
//		 x | A | B | C | D | i
//
// repstart
//      SCL	____/~~~~\___
//	SDA	__/~~~\______
//		 x | A | B | C | D | i
//
// stop	
//      SCL	____/~~~~~~~~
//	SDA	==\____/~~~~~
//		 x | A | B | C | D | i
//
//- write
//	SCL	____/~~~~\____
//	SDA	==X=========X=
//		 x | A | B | C | D | i
//
//- read
//	SCL	____/~~~~\____
//	SDA	XXXX=====XXXX
//		 x | A | B | C | D | i
//

`include "../src/params.v"

module bit_ctrl(CLK,
                RST_N, 
                CMD, 
                TXD, 
                RXD, 
                RES, 
                SCL, 
                SDA_I, 
                SDA_O, 
                SDA_OE);


input CLK, RST_N;
input [`I2C_CMD_WIDTH - 1 : 0] CMD;
input TXD;
output RXD;
output RES;

output SCL;
output SDA_O, SDA_OE;
input SDA_I;

reg SCL;
reg SDA_O, SDA_OE;
reg RXD;
reg RES;

reg scl;
reg sda_o, sda_oe;
reg rxd;
reg res;

reg [`BIT_CTRL_FSM_WIDTH - 1 : 0] curr_state, next_state;

always @(CMD or curr_state or RST_N or scl or sda_o  or sda_oe or TXD or SDA_I)
begin
  if (RST_N)
     begin
       case (curr_state) 
         `BIT_CTRL_IDLE    : begin
                               case (CMD)
                                 `I2C_CMD_NOP   : next_state <= `BIT_CTRL_IDLE;                                                  
                                 `I2C_CMD_START : next_state <= `BIT_CTRL_START_A;  
                                 `I2C_CMD_STOP  : next_state <= `BIT_CTRL_STOP_A;
                                 `I2C_CMD_WRITE : next_state <= `BIT_CTRL_WR_A;
                                 `I2C_CMD_READ  : next_state <= `BIT_CTRL_RD_A;
                                 default        : next_state <= `BIT_CTRL_IDLE;  
                               endcase    
                               scl <= scl;
                               sda_o <= sda_o;
                               sda_oe <= sda_oe;    
                               rxd <= 0;
                               res <= 0;                           
                             end
         `BIT_CTRL_START_A : begin
                               next_state <= `BIT_CTRL_START_B;
                               scl <= scl;
                               sda_o <= 1;
                               sda_oe <= sda_oe; 
                               rxd <= 0;
                               res <= 0;
                             end
         `BIT_CTRL_START_B : begin
                               next_state <= `BIT_CTRL_START_C;
                               scl <= 1;
                               sda_o <= 1;
                               sda_oe <= 1; 
                               rxd <= 0;
                               res <= 0;                                        
                             end
         `BIT_CTRL_START_C : begin
                               next_state <= `BIT_CTRL_START_D;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 1;
                               rxd <= 0;
                               res <= 0;                                          
                             end
         `BIT_CTRL_START_D : begin
                               next_state <= `BIT_CTRL_START_E;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 1;
                               rxd <= 0;
                               res <= 1;                                         
                             end
         `BIT_CTRL_START_E : begin
                               next_state <= `BIT_CTRL_IDLE;
                               scl <= 0;
                               sda_o <= 0;
                               sda_oe <= 1;
                               rxd <= 0;
                               res <= 0;                                          
                             end
         `BIT_CTRL_STOP_A  : begin
                               next_state <= `BIT_CTRL_STOP_B;
                               scl <= 0;
                               sda_o <= 0;
                               sda_oe <= 1; 
                               rxd <= 0;
                               res <= 0;                                       
                             end
         `BIT_CTRL_STOP_B  : begin
                               next_state <= `BIT_CTRL_STOP_C;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 1;     
                               rxd <= 0;
                               res <= 0;                                     
                             end
         `BIT_CTRL_STOP_C  : begin
                               next_state <= `BIT_CTRL_STOP_D;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 1;    
                               rxd <= 0;
                               res <= 1;                                      
                             end
         `BIT_CTRL_STOP_D  : begin
                               next_state <= `BIT_CTRL_IDLE;
                               scl <= 1;
                               sda_o <= 1;
                               sda_oe <= 1;
                               rxd <= 0;
                               res <= 0;                                          
                             end
         `BIT_CTRL_RD_A    : begin
                               next_state <= `BIT_CTRL_RD_B;
                               scl <= 0;
                               sda_o <= 0;
                               sda_oe <= 0;
                               rxd <= 0;
                               res <= 0;                                          
                             end
         `BIT_CTRL_RD_B    : begin
                               next_state <= `BIT_CTRL_RD_C;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 0;
                               rxd <= 0;
                               res <= 1;                                          
                             end
         `BIT_CTRL_RD_C    : begin
                               next_state <= `BIT_CTRL_RD_D;
                               scl <= 1;
                               sda_o <= 0;
                               sda_oe <= 0;
                               rxd <= SDA_I;
                               res <= 0;                                          
                             end
         `BIT_CTRL_RD_D    : begin
                               next_state <= `BIT_CTRL_IDLE;
                               scl <= 0;
                               sda_o <= 0;
                               sda_oe <= 0;  
                               rxd <= 0;
                               res <= 0;                                        
                             end
         `BIT_CTRL_WR_A    : begin
                               next_state <= `BIT_CTRL_WR_B;
                               scl <= 0;
                               sda_o <= TXD;
                               sda_oe <= 1;  
                               rxd <= 0;
                               res <= 0;                                        
                             end
         `BIT_CTRL_WR_B    : begin
                               next_state <= `BIT_CTRL_WR_C;
                               scl <= 1;
                               sda_o <= sda_o;
                               sda_oe <= 1;
                               rxd <= 0;
                               res <= 1;                                          
                             end
         `BIT_CTRL_WR_C    : begin
                               next_state <= `BIT_CTRL_WR_D;
                               scl <= 1;
                               sda_o <= sda_o;
                               sda_oe <= 1;           
                               rxd <= 0;
                               res <= 0;                               
                             end
         `BIT_CTRL_WR_D    : begin
                               next_state <= `BIT_CTRL_IDLE;
                               scl <= 0;
                               sda_o <= sda_o;
                               sda_oe <= 1;           
                               rxd <= 0;
                               res <= 0;                               
                             end
         default           : begin
                               next_state <= `BIT_CTRL_IDLE;
                               scl <= scl;
                               sda_o <= sda_o;
                               sda_oe <= sda_oe;           
                               rxd <= 0;
                               res <= 0;                               
                             end
       endcase     
     end
  else
     begin
       next_state <= `BIT_CTRL_IDLE;
       scl <= 1;
       sda_o <= 1;
       sda_oe <= 1;
       rxd <= 0;
       res <= 0;       
     end   
end       

always @(posedge CLK)
begin
  if(RST_N)
    begin
       curr_state <= next_state;
       SCL <= scl;
       SDA_O <= sda_o;
       SDA_OE <= sda_oe;    
       RXD <= rxd;
       RES <= res;
    end
  else
    begin
       curr_state <= `BIT_CTRL_IDLE;
       SCL <= 1;
       SDA_O <= 1;
       SDA_OE <= 1;
       RXD <= 0;
       RES <= 0;
    end  
end



endmodule