op_ctrl.v

Verilog for I2C core source code

                       ld <= 0; 
                       cnt_ld <= 0;
                       shift <= 0;
                       sa <= 0;
                       busy_n <= 1;
                       full <= 0;
                       empty <= 0;    
                       out_ask <= 0;                    
                       case(curr_comm)
                         `I2C_CMD_NOP   : begin
                                            next_state <= `OP_END;
                                            next_comm <= `I2C_CMD_STOP;                                                                                         
                                          end 
                         `I2C_CMD_STOP  : begin                                            
                                            if(COMM_RES)
                                              begin 
                                                next_state <= `OP_IDLE;
                                                next_comm <= `I2C_CMD_NOP;
                                              end
                                            else
                                              begin
                                                next_state <= `OP_END;
                                                next_comm <= `I2C_CMD_STOP;                                               
                                              end                                             
                                          end
                         default        : begin
                                            next_state <= `OP_IDLE;
                                            next_comm <= `I2C_CMD_NOP;                                              
                                          end                
                       endcase                          
                     end 
        default    : begin
                       next_state <= `OP_IDLE;
                       next_comm <= `I2C_CMD_NOP;
                       op_res <= 0;
                       data <= 0;
                       ld <= 0;
                       cnt_ld <= 0;
                       chk_ask <= 0;
                       out_ask <= 0;
                       shift <= 0;
                       sa <= 0;
                       busy_n <= 0;
                       full <= 0;
                       empty <= 0;                        
                     end
      endcase                                                     
    end
  else
    begin
      next_state <= `OP_IDLE;
      next_comm <= `I2C_CMD_NOP;
      op_res <= 0;
      data <= 0;
      ld <= 0;
      cnt_ld <= 0;
      busy_n <= 0;
      full <= 0;
      empty <= 0;    
      shift <= 0;
      out_ask <= 0;
      sa <= 0;
      chk_ask <= 0;   
    end  
end

always@(posedge CLK)          
begin
  if(RST_N)
    begin
      curr_state <= next_state;
      curr_comm <= next_comm;
      CMD <= next_comm;
      OP_RES <= op_res;
    end
  else
    begin
      curr_state <= `OP_IDLE;
      curr_comm <= `I2C_CMD_NOP;  
      CMD <=  `I2C_CMD_NOP; 
      OP_RES <= 0;
    end  
end  

//cnt
assign cnt_done = cnt_shift[8];
always@(posedge CLK)
begin
  if(RST_N)
    begin
      if (cnt_ld)
        begin
          cnt_shift <= 9'b0_0000_0001;
        end  
      else
        begin
         if(COMM_RES) 
           begin
             cnt_shift <= {cnt_shift[7:0],1'b0};
           end  
          else;    
        end  
    end
  else
    begin
     cnt_shift <= 0;
    end  
end

//write
always@(posedge CLK)
begin
  if(RST_N)
     out_ask1 <= out_ask;
   else
     out_ask1 <= 0; 
end
assign TXD = out_ask ? trans_done : dataout_shift[7];
always@(posedge CLK)
begin
  if(RST_N)
    begin
      if (ld)
        begin
          dataout_shift <= data;
        end  
      else
        begin
         if(COMM_RES) 
           begin
             dataout_shift <= {dataout_shift[6:0],1'b0};
           end  
          else;    
        end  
    end
  else
    begin
     dataout_shift <= 0;
    end  
end

always@(posedge CLK)
begin
  if(RST_N)
     chk_ask1 <= chk_ask;
   else
     chk_ask1 <= 0; 
end

always@(posedge CLK)
begin
  if(RST_N)
    begin
      if(chk_ask1 & comm_res)
        ASK_IN <= RXD;
      else; 
    end
  else
    begin
      ASK_IN <= 0;
    end  
end
//read
always@(posedge CLK)
begin
  if(RST_N)
     comm_res <= COMM_RES;
   else
     comm_res <= 0; 
end

always@(posedge CLK)
begin
  if(RST_N)
    begin
      if(shift & comm_res)
        datain_shift <= {datain_shift[6:0],RXD};
    end
  else
    begin
      datain_shift <= 0;
    end  
end

always @(posedge CLK)
begin
  if(RST_N)
    if(sa)
       DATA_OUT <= datain_shift;
     else;  
  else
    DATA_OUT <= 0;  
end

always @(posedge CLK)
begin
  if(RST_N)
    begin
      FULL <= full;
      EMPTY <= empty;
      BUSY_N <= busy_n;
    end
  else
    begin
      FULL <= 0;
      EMPTY <= 0;
      BUSY_N <= 1;
    end  
end
//传输数目计数器
always@(posedge CLK)
begin
  if(RST_N)
    begin
      if (op_res)
        cnt <= OP_NUM;
      else
        if (empty | full)
           cnt <= cnt - 1;
      trans_done <= DIR ? (cnt == 0) : (cnt == 1);     
    end
  else
    begin
      cnt <= 0;
      trans_done <= 1;
    end  
end


endmodule