params.v

Verilog for I2C core source code

`timescale 1ns / 100ps
//bit控制命令编码
//可根据情况，自定义编码方式
`define I2C_CMD_WIDTH 3
`define I2C_CMD_NOP   3'b000
`define I2C_CMD_START 3'b001
`define I2C_CMD_STOP  3'b010
`define I2C_CMD_WRITE 3'b011
`define I2C_CMD_READ  3'b100
//bit ctrl 状态机编码
//可根据情况，自定义编码方式
`define BIT_CTRL_FSM_WIDTH 5
`define BIT_CTRL_IDLE     0
`define BIT_CTRL_START_A  1
`define BIT_CTRL_START_B  2
`define BIT_CTRL_START_C  3
`define BIT_CTRL_START_D  4
`define BIT_CTRL_START_E  5
`define BIT_CTRL_STOP_A   6
`define BIT_CTRL_STOP_B   7
`define BIT_CTRL_STOP_C   8
`define BIT_CTRL_STOP_D   9
`define BIT_CTRL_RD_A     10
`define BIT_CTRL_RD_B     11
`define BIT_CTRL_RD_C     12
`define BIT_CTRL_RD_D     13
`define BIT_CTRL_WR_A     14
`define BIT_CTRL_WR_B     15
`define BIT_CTRL_WR_C     16
`define BIT_CTRL_WR_D     17

//op_ctrl 状态机编码
`define OP_WIDTH          3
 
`define OP_IDLE           0
`define OP_START          1
`define OP_DADDR          2
`define OP_TADDR          3
`define OP_DATA_W         4
`define OP_READDR         5
`define OP_DATA_R         6
`define OP_END            7