interface.v

Verilog for I2C core source code

/*********************************************************************
File name: 		  interface.v
Module name:	          interface	
Author:		         atuhappy( 陈亮)
Email：                  [e-mail]    
Version:			1.0
Date:				2004.7.26


Function Description:
和host接口
						
*********************************************************************/

`include "../src/params.v"
module interface(CLK,
                 RST_N,
                 CS,
                 ADDR,
                 WR,
                 RD,
                 HOST_DIN,
                 HOST_DOUT,
                 INT,       //中断信号(FULL or  EMPTY) 
                 OP_REQ,    //启动一次数据传输
                 OP_RES,
                 OP_NUM,    //发送或接收的字节数(OP_NUM+1)
                 DIR,       //1 wr 0 rd
                 DEVICE,    //访问器件地址
                 TARGET,    //访问器件的内部地址，如ram地址
                 BUSY_N,    //正在进行数据读写
                 ASK_IN,    //外设返回的ask
                 DATA_OUT,  //发送缓冲区
                 DATA_IN,   //接收缓冲区
                 FULL,      //产生一个高脉冲，表示接收缓冲区（DATA_OUT）已满
                 EMPTY);    //产生一个高脉冲，表示发送缓冲区（DATA_IN）已空
                  

input CLK, RST_N, CS;
input [2 : 0] ADDR;
input WR, RD;
input [7 : 0] HOST_DIN;
output [7 : 0] HOST_DOUT;
output INT;
output  OP_REQ;
input  OP_RES;
output [7 :0] OP_NUM;
output DIR;
output [6 : 0] DEVICE;
output [7 : 0] TARGET;
input BUSY_N;
input ASK_IN;
input [7 : 0] DATA_IN;
output [7 : 0] DATA_OUT;    
input FULL, EMPTY;

reg INT;
reg [6 : 0] DEVICE;
reg [7 : 0] TARGET;
reg [7 : 0] DATA_OUT;
reg [7 :0] OP_NUM;
reg [7 : 0] HOST_DOUT;

reg [7 : 0] CTRL_REG;  //控制寄存器
reg [7 : 0] STU_REG;   //状态寄存器




assign DIR = CTRL_REG[1]; 
assign OP_REQ = CTRL_REG[0];   

always@(posedge CLK)
begin
  if(RST_N)
    INT <= FULL | EMPTY;
  else
    INT <= 0;  
end

always@(posedge CLK)
begin
  if(RST_N)
    STU_REG[3] <= BUSY_N;
  else
    STU_REG[3] <= 0;  
end

always@(posedge CLK)
begin
  if(RST_N) 
    begin
      if(CS & WR)
        begin
          case(ADDR)
          0  : DEVICE <= HOST_DIN[6 : 0];
          1  : TARGET <= HOST_DIN;
          2  : OP_NUM <= HOST_DIN;
          3  : begin
                 DATA_OUT <= HOST_DIN;
                 STU_REG[0] <= 0;
               end  
          4  : STU_REG[2] <= 0;     
          5  : CTRL_REG <= HOST_DIN[1 : 0];
          default :;
          endcase;  
        end
      else
        begin
          if(OP_RES)
            CTRL_REG[0] <= 0;
          else
            if(EMPTY)
              STU_REG[0] <= 1;
            else
              if(ASK_IN) 
                 STU_REG[2] <= 1;   
               else;    
        end  
    end
  else
    begin
      DEVICE <= 0;
      TARGET <= 0;
      DATA_OUT <= 0;  
      OP_NUM <= 1;
      CTRL_REG <= 0;
      STU_REG[7 : 4] <= 0;
      STU_REG[2] <= 0;
      STU_REG[0] <= 0; 
    end  
end

always@(posedge CLK)
begin
  if(RST_N)
    begin
      if(CS & RD)
        begin
          case(ADDR)
          3 : begin
                HOST_DOUT <= DATA_IN;
                STU_REG[1] <= 0;                
              end
          4 : HOST_DOUT <= STU_REG;
          5 : HOST_DOUT <= CTRL_REG;     
          default : ;
          endcase    
        end
      else
        begin
          if(FULL)
             STU_REG[1] <= 1;   
           else;       
        end  
    end
  else
    begin
      HOST_DOUT <= 8'bzzzz_zzzz; 
      STU_REG[1] <= 0; 
    end  
 end


endmodule