i2c_master.v

Verilog for I2C core source code

/*********************************************************************
File name: 		  i2c_master.v
Module name:	          i2c_master	
Author:		         atuhappy( 陈亮)
Email：                  [e-mail]    
Version:			1.0
Date:				2004.7.27


Function Description:
I2C Master Core的顶层模块
						
*********************************************************************/
`include "../src/params.v"
module i2c_master(CLK,
                  RST_N,
                  CS,
                  ADDR,
                  WR,
                  RD,
                  HOST_DIN,
                  HOST_DOUT,
                  INT,
                  SCL,
                  SDA_I,
                  SDA_O,
                  SDA_OE);

input CLK, RST_N, CS;
input [2 : 0] ADDR;
input WR, RD;
input [7 : 0] HOST_DIN;
output [7 : 0] HOST_DOUT;
output INT;
output SCL;
output SDA_O, SDA_OE;
input SDA_I;


wire op_req;
wire op_res;
wire dir;
wire [6:0] device;
wire [7:0] target;
wire [7:0] data_in;
wire [7:0] data_out;
wire busy_n;
wire full, empty;
wire ask_in;
wire [7 : 0] op_num;
wire [`I2C_CMD_WIDTH - 1 : 0] cmd;
wire txd,rxd;


interface    i_f(.CLK              ( CLK       ),
                 .RST_N            ( RST_N     ),
                 .CS               ( CS        ),
                 .ADDR             ( ADDR      ),
                 .WR               ( WR        ),
                 .RD               ( RD        ),
                 .HOST_DIN         ( HOST_DIN  ),
                 .HOST_DOUT        ( HOST_DOUT ),
                 .INT              ( INT       ), 
                 .OP_REQ           ( op_req    ),    
                 .OP_RES           ( op_res    ),
                 .OP_NUM           ( op_num    ),   
                 .DIR              ( dir       ),      
                 .DEVICE           ( device    ),    
                 .TARGET           ( target    ),    
                 .BUSY_N           ( busy_n    ),    
                 .ASK_IN           ( ask_in    ),   
                 .DATA_OUT         ( data_in   ),  
                 .DATA_IN          ( data_out  ),   
                 .FULL             ( full      ),      
                 .EMPTY            ( empty     ));    

op_ctrl       oc(.CLK               ( CLK       ),
                 .RST_N             ( RST_N     ),
                 .OP_REQ            ( op_req    ),     
                 .OP_RES            ( op_res    ),
                 .OP_NUM            ( op_num    ), 
                 .DIR               ( dir       ),       
                 .DEVICE            ( device    ),    
                 .TARGET            ( target    ),  
                 .BUSY_N            ( busy_n    ),  
                 .ASK_IN            ( ask_in    ),
                 .DATA_IN           ( data_in   ),
                 .DATA_OUT          ( data_out  ),
                 .FULL              ( full      ),      
                 .EMPTY             ( empty     ),                     
                 .CMD               ( cmd       ),
                 .COMM_RES          ( res       ),
                 .TXD               ( txd       ),
                 .RXD               ( rxd       ));
                 
bit_ctrl   bc  (.CLK       ( CLK        ),
                .RST_N     ( RST_N      ), 
                .CMD       ( cmd        ),  
                .TXD       ( txd        ), 
                .RXD       ( rxd        ), 
                .RES       ( res        ), 
                .SCL       ( SCL        ), 
                .SDA_I     ( SDA_I      ), 
                .SDA_O     ( SDA_O      ), 
                .SDA_OE    ( SDA_OE     ));   
                
 

endmodule