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📄 prev_cmp_original_signal.qmsg

📁 一种基于LUT的预失真方法。其中的一部分
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{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[26\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[26\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[25\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[25\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[24\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[24\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[22\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[22\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[20\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[20\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[19\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[19\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[17\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[17\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[16\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[16\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[14\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[14\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[12\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[12\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[11\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[11\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[8\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[8\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[7\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[7\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[6\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[6\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[3\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[3\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[2\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[2\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[1\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[1\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[0\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[0\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[4\] dds2ch:inst3\|accl:U_accl\|rFREQ\[5\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[4\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[5\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[5\] dds2ch:inst3\|accl:U_accl\|rFREQ\[9\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[5\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[9\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[9\] dds2ch:inst3\|accl:U_accl\|rFREQ\[10\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[9\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[10\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[10\] dds2ch:inst3\|accl:U_accl\|rFREQ\[13\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[10\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[13\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[13\] dds2ch:inst3\|accl:U_accl\|rFREQ\[15\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[13\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[15\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[15\] dds2ch:inst3\|accl:U_accl\|rFREQ\[18\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[15\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[18\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[18\] dds2ch:inst3\|accl:U_accl\|rFREQ\[21\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[18\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[21\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[21\] dds2ch:inst3\|accl:U_accl\|rFREQ\[23\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[21\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[23\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[23\] dds2ch:inst3\|accl:U_accl\|rFREQ\[27\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[23\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[27\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|rFREQ\[27\] dds2ch:inst3\|accl:U_accl\|rFREQ\[30\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[27\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[30\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|subround1 dds2ch:inst3\|muad:U_muad\|round1 " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|subround1\" merged to single register \"dds2ch:inst3\|muad:U_muad\|round1\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 800 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|subround2 dds2ch:inst3\|muad:U_muad\|round2 " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|subround2\" merged to single register \"dds2ch:inst3\|muad:U_muad\|round2\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 800 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[0\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[0\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[0\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[0\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[1\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[1\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[1\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[1\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[2\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[2\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[2\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[2\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[3\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[3\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[3\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[3\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[4\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[4\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[4\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[4\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[5\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[5\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[5\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[5\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[6\] dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[6\] " "Info: Duplicate register \"dds2ch:inst3\|muad:U_muad\|mult:U_mult\|reg_a\[6\]\" merged to single register \"dds2ch:inst3\|muad:U_muad\|mult:U1_mult\|reg_a\[6\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1132 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|phout\[1\] dds2ch:inst3\|accl:U_accl\|phout\[0\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|phout\[1\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|phout\[0\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 254 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|phout\[2\] dds2ch:inst3\|accl:U_accl\|phout\[0\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|phout\[2\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|phout\[0\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 254 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "dds2ch:inst3\|accl:U_accl\|phout\[3\] dds2ch:inst3\|accl:U_accl\|phout\[0\] " "Info: Duplicate register \"dds2ch:inst3\|accl:U_accl\|phout\[3\]\" merged to single register \"dds2ch:inst3\|accl:U_accl\|phout\[0\]\"" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 254 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|phout\[0\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|phout\[0\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 254 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "5 " "Info: Inferred 5 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "FIRInterp:inst8\|mem~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"FIRInterp:inst8\|mem~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Info: Parameter OPERATION_MODE set to DUAL_PORT" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Info: Parameter WIDTH_A set to 32" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 4 " "Info: Parameter WIDTHAD_A set to 4" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 16 " "Info: Parameter NUMWORDS_A set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 32 " "Info: Parameter WIDTH_B set to 32" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 4 " "Info: Parameter WIDTHAD_B set to 4" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 16 " "Info: Parameter NUMWORDS_B set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Info: Parameter OUTDATA_REG_B set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Info: Parameter ADDRESS_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Info: Parameter OUTDATA_ACLR_B set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Info: Parameter ADDRESS_REG_B set to CLOCK0" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "FIR/FIRInterp.v" "mem~0" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 14 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "dds2ch:inst3\|romwl:U_romwl\|Ram0~32 " "Info: Inferred altsyncram megafunction from the following design logic: \"dds2ch:inst3\|romwl:U_romwl\|Ram0~32\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 26 " "Info: Parameter WIDTH_A set to 26" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 7 " "Info: Parameter WIDTHAD_A set to 7" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 128 " "Info: Parameter NUMWORDS_A set to 128" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/rom0_romwl_ea2271f9.hdl.mif " "Info: Parameter INIT_FILE set to db/rom0_romwl_ea2271f9.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "dds2ch.v" "Ram0~32" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 550 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "dds2ch:inst3\|romcl:U_romcl\|Ram0~22 " "Info: Inferred altsyncram megafunction from the following design logic: \"dds2ch:inst3\|romcl:U_romcl\|Ram0~22\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 16 " "Info: Parameter WIDTH_A set to 16" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 7 " "Info: Parameter WIDTHAD_A set to 7" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 128 " "Info: Parameter NUMWORDS_A set to 128" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/rom0_romcl_f514e9aa.hdl.mif " "Info: Parameter INIT_FILE set to db/rom0_romcl_f514e9aa.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "dds2ch.v" "Ram0~22" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 393 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "FIRInterp:inst8\|MyCofRom:CofTab\|Ram0~25 " "Info: Inferred altsyncram megafunction from the following design logic: \"FIRInterp:inst8\|MyCofRom:CofTab\|Ram0~25\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 18 " "Info: Parameter WIDTH_A set to 18" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 8 " "Info: Parameter WIDTHAD_A set to 8" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 256 " "Info: Parameter NUMWORDS_A set to 256" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/rom0_MyCofRom_8f2fad26.hdl.mif " "Info: Parameter INIT_FILE set to db/rom0_MyCofRom_8f2fad26.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "FIR/MyCofRom.v" "Ram0~25" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/MyCofRom.v" 11 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "datarom:inst\|OFDMrom_center_167:myrom\|Ram0~42 " "Info: Inferred altsyncram megafunction from the following design logic: \"datarom:inst\|OFDMrom_center_167:myrom\|Ram0~42\"" { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Info: Parameter WIDTH_A set to 32" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 11 " "Info: Parameter WIDTHAD_A set to 11" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 2048 " "Info: Parameter NUMWORDS_A set to 2048" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE AUTO " "Info: Parameter RAM_BLOCK_TYPE set to AUTO" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/rom0_OFDMrom_center_167_51e0f9e1.hdl.mif " "Info: Parameter INIT_FILE set to db/rom0_OFDMrom_center_167_51e0f9e1.hdl.mif" {  } {  } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0}  } { { "OFDMrom_center_167.v" "Ram0~42" { Text "E:/Graduation_Design/Quartus/original_signal/OFDMrom_center_167.v" 9 -1 0 } }  } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0}
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