📄 original_signal.map.rpt
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+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 738 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 78 ;
; Number of registers using Asynchronous Clear ; 587 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 176 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
; 3:1 ; 34 bits ; 68 LEs ; 34 LEs ; 34 LEs ; Yes ; |original_signal|FIRInterp:inst8|LTDt[2] ;
; 4:1 ; 34 bits ; 68 LEs ; 34 LEs ; 34 LEs ; Yes ; |original_signal|FIRInterp:inst8|RTDt[18] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------+
+--------------------------------------------------------------------------------------------+
; Source assignments for FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated ;
+---------------------------------+--------------------+------+------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------------------+
+-------------------------------------------------------------------------------------------------------+
; Source assignments for dds2ch:inst3|romwl:U_romwl|altsyncram:Ram0_rtl_1|altsyncram_mtv:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------+
+-------------------------------------------------------------------------------------------------------+
; Source assignments for dds2ch:inst3|romcl:U_romcl|altsyncram:Ram0_rtl_2|altsyncram_guv:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------+
+-------------------------------------------------------------------------------------------------------------+
; Source assignments for FIRInterp:inst8|MyCofRom:CofTab|altsyncram:Ram0_rtl_3|altsyncram_7901:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------+
; Source assignments for datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+-----------------------------------------------------+
+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds2ch:inst3 ;
+----------------+-------+----------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------+
; FREQ_BITS ; 32 ; Untyped ;
; DATA_BITS ; 14 ; Untyped ;
; U_BITS ; 17 ; Untyped ;
; ADDR_M ; 7 ; Untyped ;
; ADDR_N ; 7 ; Untyped ;
; WAVE_BITS ; 13 ; Untyped ;
; COEFF_BITS ; 8 ; Untyped ;
; INTER_BITS ; 7 ; Untyped ;
+----------------+-------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-----------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds2ch:inst3|accl:U_accl ;
+----------------+-------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+----------------------------------------------+
; FREQ_BITS ; 32 ; Signed Integer ;
; U_BITS ; 17 ; Signed Integer ;
+----------------+-------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds2ch:inst3|bctrl:U_bctrl ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; U_BITS ; 17 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds2ch:inst3|inverter:U_inverter ;
+----------------+-------+------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------------+
; U_BITS ; 17 ; Signed Integer ;
; ADDR_M ; 7 ; Signed Integer ;
; ADDR_N ; 7 ; Signed Integer ;
+----------------+-------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: dds2ch:inst3|romwl:U_romwl ;
+----------------+-------+------------------------------------------------+
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