📄 original_signal.map.rpt
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; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II/Cyclone III ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto RAM to Logic Cell Conversion ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Use smart compilation ; Off ; Off ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
; FIR/MyCofRom.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/FIR/MyCofRom.v ;
; FIR/FIRInterp.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v ;
; datarom.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/datarom.v ;
; CLK_ALL_GEN.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v ;
; dds2ch.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/dds2ch.v ;
; frecontr.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/frecontr.v ;
; mod.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/mod.v ;
; original_signal.bdf ; yes ; User Block Diagram/Schematic File ; E:/Graduation_Design/Quartus/original_signal/original_signal.bdf ;
; OFDMrom_center_167.v ; yes ; User Verilog HDL File ; E:/Graduation_Design/Quartus/original_signal/OFDMrom_center_167.v ;
; altpll0.v ; yes ; Other ; E:/Graduation_Design/Quartus/original_signal/altpll0.v ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altpll.tdf ;
; aglobal71.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/aglobal71.inc ;
; stratix_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratixii_pll.inc ;
; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/cycloneii_pll.inc ;
; db/altpll_ena1.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf ;
; altsyncram.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf ;
; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_mux.inc ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_decode.inc ;
; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/a_rdenreg.inc ;
; altrom.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altrom.inc ;
; altram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altram.inc ;
; altdpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altdpram.inc ;
; altqpram.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altqpram.inc ;
; db/altsyncram_csi1.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altsyncram_csi1.tdf ;
; db/altsyncram_mtv.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altsyncram_mtv.tdf ;
; db/altsyncram_guv.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altsyncram_guv.tdf ;
; db/altsyncram_7901.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altsyncram_7901.tdf ;
; db/altsyncram_g511.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/altsyncram_g511.tdf ;
; lpm_mult.tdf ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_mult.tdf ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; multcore.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/multcore.inc ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; Megafunction ; c:/altera/71/quartus/libraries/megafunctions/altshift.inc ;
; db/mult_mo01.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/mult_mo01.tdf ;
; db/mult_jr01.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/mult_jr01.tdf ;
; db/mult_jv01.tdf ; yes ; Auto-Generated Megafunction ; E:/Graduation_Design/Quartus/original_signal/db/mult_jv01.tdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------+
+----------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+------------+
; Resource ; Usage ;
+---------------------------------------------+------------+
; Estimated Total logic elements ; 738 ;
; ; ;
; Total combinational functions ; 392 ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 4 ;
; -- 3 input functions ; 230 ;
; -- <=2 input functions ; 158 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 180 ;
; -- arithmetic mode ; 212 ;
; ; ;
; Total registers ; 738 ;
; -- Dedicated logic registers ; 738 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 15 ;
; Total memory bits ; 76032 ;
; Embedded Multiplier 9-bit elements ; 6 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; RstN~input ;
; Maximum fan-out ; 642 ;
; Total fan-out ; 4632 ;
; Average fan-out ; 3.58 ;
+---------------------------------------------+------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------------------+--------------+
; |original_signal ; 392 (1) ; 738 (0) ; 76032 ; 6 ; 4 ; 1 ; 15 ; 0 ; |original_signal ; work ;
; |CLK_ALL_GEN:inst5| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |original_signal|CLK_ALL_GEN:inst5 ; work ;
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