original_signal.map.rpt

一种基于LUT的预失真方法。其中的一部分

Analysis & Synthesis report for original_signal
Sun Nov 25 20:53:27 2007
Quartus II Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Analysis & Synthesis DSP Block Usage Summary
  9. Registers Removed During Synthesis
 10. General Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Source assignments for FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated
 13. Source assignments for dds2ch:inst3|romwl:U_romwl|altsyncram:Ram0_rtl_1|altsyncram_mtv:auto_generated
 14. Source assignments for dds2ch:inst3|romcl:U_romcl|altsyncram:Ram0_rtl_2|altsyncram_guv:auto_generated
 15. Source assignments for FIRInterp:inst8|MyCofRom:CofTab|altsyncram:Ram0_rtl_3|altsyncram_7901:auto_generated
 16. Source assignments for datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated
 17. Parameter Settings for User Entity Instance: dds2ch:inst3
 18. Parameter Settings for User Entity Instance: dds2ch:inst3|accl:U_accl
 19. Parameter Settings for User Entity Instance: dds2ch:inst3|bctrl:U_bctrl
 20. Parameter Settings for User Entity Instance: dds2ch:inst3|inverter:U_inverter
 21. Parameter Settings for User Entity Instance: dds2ch:inst3|romwl:U_romwl
 22. Parameter Settings for User Entity Instance: dds2ch:inst3|romcl:U_romcl
 23. Parameter Settings for User Entity Instance: dds2ch:inst3|mux:U_mux
 24. Parameter Settings for User Entity Instance: dds2ch:inst3|muad:U_muad
 25. Parameter Settings for User Entity Instance: dds2ch:inst3|muad:U_muad|delayl:U_delayl
 26. Parameter Settings for User Entity Instance: dds2ch:inst3|out:U_out
 27. Parameter Settings for User Entity Instance: frecontr:inst2
 28. Parameter Settings for User Entity Instance: altpll0:inst6|altpll:altpll_component
 29. Parameter Settings for User Entity Instance: FIRInterp:inst8
 30. Parameter Settings for Inferred Entity Instance: FIRInterp:inst8|altsyncram:mem_rtl_0
 31. Parameter Settings for Inferred Entity Instance: dds2ch:inst3|romwl:U_romwl|altsyncram:Ram0_rtl_1
 32. Parameter Settings for Inferred Entity Instance: dds2ch:inst3|romcl:U_romcl|altsyncram:Ram0_rtl_2
 33. Parameter Settings for Inferred Entity Instance: FIRInterp:inst8|MyCofRom:CofTab|altsyncram:Ram0_rtl_3
 34. Parameter Settings for Inferred Entity Instance: datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4
 35. Parameter Settings for Inferred Entity Instance: mod:inst4|lpm_mult:Mult1
 36. Parameter Settings for Inferred Entity Instance: mod:inst4|lpm_mult:Mult0
 37. Parameter Settings for Inferred Entity Instance: FIRInterp:inst8|lpm_mult:Mult0
 38. Parameter Settings for Inferred Entity Instance: dds2ch:inst3|muad:U_muad|mult:U1_mult|lpm_mult:Mult0
 39. Parameter Settings for Inferred Entity Instance: dds2ch:inst3|muad:U_muad|mult:U_mult|lpm_mult:Mult0
 40. lpm_mult Parameter Settings by Entity Instance
 41. Analysis & Synthesis Messages
 42. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                       ;
+------------------------------------+-----------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Nov 25 20:53:27 2007         ;
; Quartus II Version                 ; 7.1 Build 178 06/25/2007 SP 1 SJ Full Version ;
; Revision Name                      ; original_signal                               ;
; Top-level Entity Name              ; original_signal                               ;
; Family                             ; Cyclone III                                   ;
; Total logic elements               ; 738                                           ;
;     Total combinational functions  ; 392                                           ;
;     Dedicated logic registers      ; 738                                           ;
; Total registers                    ; 738                                           ;
; Total pins                         ; 15                                            ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 76,032                                        ;
; Embedded Multiplier 9-bit elements ; 6                                             ;
; Total PLLs                         ; 1                                             ;
+------------------------------------+-----------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP3C25Q240C8       ;                    ;
; Top-level entity name                                                          ; original_signal    ; original_signal    ;
; Family name                                                                    ; Cyclone III        ; Stratix II         ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;