altpll_ena1.tdf

一种基于LUT的预失真方法。其中的一部分

--altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=3125 clk0_duty_cycle=50 clk0_multiply_by=4096 clk0_phase_shift="0" clk1_divide_by=3125 clk1_duty_cycle=50 clk1_multiply_by=8192 clk1_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone III" inclk0_input_frequency=20000 intended_device_family="Cyclone III" operation_mode="normal" pll_type="FAST" port_phasecounterselect="PORT_UNUSED" width_clock=5 clk inclk phasecounterselect
--VERSION_BEGIN 7.1SP1 cbx_altpll 2007:03:22:15:47:52:SJ cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_mgl 2007:06:11:08:05:04:SJ cbx_stratixii 2007:02:12:17:08:26:SJ cbx_util_mgl 2007:01:15:12:22:48:SJ  VERSION_END


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PARAMETERS
(
	CLKOUT_WIDTH = 5,
	PHASECOUNTERSELECT_WIDTH = 3
);
FUNCTION cycloneiii_pll (areset, clkswitch, configupdate, fbin, inclk[1..0], pfdena, phasecounterselect[phasecounterselect_width-1..0], phasestep, phaseupdown, scanclk, scanclkena, scandata)
WITH ( 	BANDWIDTH,	BANDWIDTH_TYPE,	C0_HIGH,	C0_INITIAL,	C0_LOW,	C0_MODE,	C0_PH,	C0_TEST_SOURCE,	C1_HIGH,	C1_INITIAL,	C1_LOW,	C1_MODE,	C1_PH,	C1_TEST_SOURCE,	C1_USE_CASC_IN,	C2_HIGH,	C2_INITIAL,	C2_LOW,	C2_MODE,	C2_PH,	C2_TEST_SOURCE,	C2_USE_CASC_IN,	C3_HIGH,	C3_INITIAL,	C3_LOW,	C3_MODE,	C3_PH,	C3_TEST_SOURCE,	C3_USE_CASC_IN,	C4_HIGH,	C4_INITIAL,	C4_LOW,	C4_MODE,	C4_PH,	C4_TEST_SOURCE,	C4_USE_CASC_IN,	CHARGE_PUMP_CURRENT,	CHARGE_PUMP_CURRENT_BITS,	CLK0_COUNTER,	CLK0_DIVIDE_BY,	CLK0_DUTY_CYCLE,	CLK0_MULTIPLY_BY,	CLK0_OUTPUT_FREQUENCY,	CLK0_PHASE_SHIFT,	CLK0_PHASE_SHIFT_NUM,	clk0_use_even_counter_mode,	clk0_use_even_counter_value,	CLK1_COUNTER,	CLK1_DIVIDE_BY,	CLK1_DUTY_CYCLE,	CLK1_MULTIPLY_BY,	CLK1_OUTPUT_FREQUENCY,	CLK1_PHASE_SHIFT,	CLK1_PHASE_SHIFT_NUM,	clk1_use_even_counter_mode,	clk1_use_even_counter_value,	CLK2_COUNTER,	CLK2_DIVIDE_BY,	CLK2_DUTY_CYCLE,	CLK2_MULTIPLY_BY,	CLK2_OUTPUT_FREQUENCY,	CLK2_PHASE_SHIFT,	CLK2_PHASE_SHIFT_NUM,	clk2_use_even_counter_mode,	clk2_use_even_counter_value,	CLK3_COUNTER,	CLK3_DIVIDE_BY,	CLK3_DUTY_CYCLE,	CLK3_MULTIPLY_BY,	CLK3_OUTPUT_FREQUENCY,	CLK3_PHASE_SHIFT,	CLK3_PHASE_SHIFT_NUM,	clk3_use_even_counter_mode,	clk3_use_even_counter_value,	CLK4_COUNTER,	CLK4_DIVIDE_BY,	CLK4_DUTY_CYCLE,	CLK4_MULTIPLY_BY,	CLK4_OUTPUT_FREQUENCY,	CLK4_PHASE_SHIFT,	CLK4_PHASE_SHIFT_NUM,	clk4_use_even_counter_mode,	clk4_use_even_counter_value,	COMPENSATE_CLOCK,	INCLK0_INPUT_FREQUENCY,	INCLK1_INPUT_FREQUENCY,	LOCK_HIGH,	LOCK_LOW,	lock_window_ui,	LOOP_FILTER_C,	LOOP_FILTER_C_BITS,	LOOP_FILTER_R,	LOOP_FILTER_R_BITS,	M,	M_INITIAL,	M_PH,	M_TEST_SOURCE,	N,	OPERATION_MODE,	PFD_MAX,	PFD_MIN,	PLL_COMPENSATION_DELAY,	PLL_TYPE,	self_reset_on_loss_lock,	SIMULATION_TYPE,	SWITCH_OVER_TYPE,	USE_DC_COUPLING,	VCO_CENTER,	VCO_DIVIDE_BY,	vco_frequency_control,	VCO_MAX,	VCO_MIN,	VCO_MULTIPLY_BY,	vco_phase_shift_step,	VCO_POST_SCALE) 
RETURNS ( activeclock, clk[CLKOUT_WIDTH-1..0], clkbad[1..0], fbout, locked, phasedone, scandataout, scandone, vcooverrange, vcounderrange);

--synthesis_resources = cycloneiii_pll 1 
SUBDESIGN altpll_ena1
( 
	clk[4..0]	:	output;
	inclk[1..0]	:	input;
	phasecounterselect[3..0]	:	input;
) 
VARIABLE 
	pll1 : cycloneiii_pll
		WITH (
			BANDWIDTH_TYPE = "auto",
			CLK0_DIVIDE_BY = 3125,
			CLK0_DUTY_CYCLE = 50,
			CLK0_MULTIPLY_BY = 4096,
			CLK0_PHASE_SHIFT = "0",
			CLK1_DIVIDE_BY = 3125,
			CLK1_DUTY_CYCLE = 50,
			CLK1_MULTIPLY_BY = 8192,
			CLK1_PHASE_SHIFT = "0",
			COMPENSATE_CLOCK = "clk0",
			INCLK0_INPUT_FREQUENCY = 20000,
			OPERATION_MODE = "normal",
			PLL_TYPE = "fast"
		);

BEGIN 
	pll1.fbin = pll1.fbout;
	pll1.inclk[] = inclk[];
	clk[] = pll1.clk[];
END;
--VALID FILE