original_signal.map.qmsg

一种基于LUT的预失真方法。其中的一部分

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 frecontr.v(35) " "Warning (10230): Verilog HDL assignment warning at frecontr.v(35): truncated value with size 32 to match size of target (6)" {  } { { "frecontr.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/frecontr.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "altpll0.v 1 1 " "Warning: Using design file altpll0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 altpll0 " "Info: Found entity 1: altpll0" {  } { { "altpll0.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/altpll0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll0 altpll0:inst6 " "Info: Elaborating entity \"altpll0\" for hierarchy \"altpll0:inst6\"" {  } { { "original_signal.bdf" "inst6" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { -72 240 496 104 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 462 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll0:inst6\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"altpll0:inst6\|altpll:altpll_component\"" {  } { { "altpll0.v" "altpll_component" { Text "E:/Graduation_Design/Quartus/original_signal/altpll0.v" 92 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll0:inst6\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"altpll0:inst6\|altpll:altpll_component\"" {  } { { "altpll0.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/altpll0.v" 92 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_ena1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altpll_ena1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_ena1 " "Info: Found entity 1: altpll_ena1" {  } { { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_ena1 altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated " "Info: Elaborating entity \"altpll_ena1\" for hierarchy \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 859 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mod mod:inst4 " "Info: Elaborating entity \"mod\" for hierarchy \"mod:inst4\"" {  } { { "original_signal.bdf" "inst4" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { 320 920 1072 480 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FIRInterp FIRInterp:inst8 " "Info: Elaborating entity \"FIRInterp\" for hierarchy \"FIRInterp:inst8\"" {  } { { "original_signal.bdf" "inst8" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { 240 152 432 368 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "MyCofRom FIRInterp:inst8\|MyCofRom:CofTab " "Info: Elaborating entity \"MyCofRom\" for hierarchy \"FIRInterp:inst8\|MyCofRom:CofTab\"" {  } { { "FIR/FIRInterp.v" "CofTab" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 77 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLK_ALL_GEN CLK_ALL_GEN:inst5 " "Info: Elaborating entity \"CLK_ALL_GEN\" for hierarchy \"CLK_ALL_GEN:inst5\"" {  } { { "original_signal.bdf" "inst5" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { -40 664 800 152 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "datarom datarom:inst " "Info: Elaborating entity \"datarom\" for hierarchy \"datarom:inst\"" {  } { { "original_signal.bdf" "inst" { Schematic "E:/Graduation_Design/Quartus/original_signal/original_signal.bdf" { { 40 -40 88 136 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "OFDMrom_center_167 datarom:inst\|OFDMrom_center_167:myrom " "Info: Elaborating entity \"OFDMrom_center_167\" for hierarchy \"datarom:inst\|OFDMrom_center_167:myrom\"" {  } { { "datarom.v" "myrom" { Text "E:/Graduation_Design/Quartus/original_signal/datarom.v" 17 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "datab U1_add 7 13 " "Warning: Port \"datab\" on the entity instantiation of \"U1_add\" is connected to a signal of width 7. The formal width of the signal in the module is 13.  Extra bits will be driven by GND." {  } { { "dds2ch.v" "U1_add" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 875 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "datab U1_sub 7 13 " "Warning: Port \"datab\" on the entity instantiation of \"U1_sub\" is connected to a signal of width 7. The formal width of the signal in the module is 13.  Extra bits will be driven by GND." {  } { { "dds2ch.v" "U1_sub" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 869 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "datab U_sub 7 13 " "Warning: Port \"datab\" on the entity instantiation of \"U_sub\" is connected to a signal of width 7. The formal width of the signal in the module is 13.  Extra bits will be driven by GND." {  } { { "dds2ch.v" "U_sub" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 863 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "datab U_add 7 13 " "Warning: Port \"datab\" on the entity instantiation of \"U_add\" is connected to a signal of width 7. The formal width of the signal in the module is 13.  Extra bits will be driven by GND." {  } { { "dds2ch.v" "U_add" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 857 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[31\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[31\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[29\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[29\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "dds2ch:inst3\|accl:U_accl\|rFREQ\[28\] data_in GND " "Warning: Reduced register \"dds2ch:inst3\|accl:U_accl\|rFREQ\[28\]\" with stuck data_in port to stuck value GND" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 204 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}