firhb.v

一种基于LUT的预失真方法。其中的一部分

module FIRHB(RST,LDin,RDin,sysClk,LDout,RDout,DOutclk,DInclk);
input RST,sysClk;
input signed[15:0] LDin,RDin;
output DOutclk,DInclk;
output signed[15:0] LDout,RDout;

reg signed[15:0] RDout,LDout;
reg DOutclk,DInclk;

reg signed[15:0] LBDT,RBDT;
wire signed[15:0] LBD1,RBD1,LBD2,RBD2,wcof1,wcof2;
reg signed[30:0] LTDt1,RTDt1,LTDt2,RTDt2;
reg signed[15:0] LDoutBuf,RDoutBuf;

reg[4:0] PhaseCnt;    //the Global phase counter 
reg[4:0] Buf1P; //the point to the write address of Buf1
reg[3:0] Buf2P;	//the point to the write address of Buf2 
wire[4:0] Addr1;
wire[3:0] Addr2;
reg we2;

assign Addr1=Buf1P+PhaseCnt;
assign Addr2=Buf2P+PhaseCnt[3:0];

always@(posedge sysClk or posedge RST) begin
		if(RST) begin
			LTDt1<=0;RTDt1<=0;RDoutBuf<=0;LDoutBuf<=0;
			Buf1P<=0;Buf2P<=0;
			PhaseCnt<=0;DOutclk<=0;
		end
		else begin
			PhaseCnt<=PhaseCnt+5'h1;
			
			if(PhaseCnt==5'h1f) begin
				Buf1P<=Buf1P+5'h1;
				DInclk<=1'b1;
			end
			else begin
				DInclk<=1'b0;
			end
			if(PhaseCnt==5'h1) begin
				LTDt1<=(LBD1)*wcof1;
				RTDt1<=(RBD1)*wcof1;
			end
			else begin
				LTDt1<=LTDt1+(LBD1)*wcof1;
				RTDt1<=RTDt1+(RBD1)*wcof1;
			end
			if(PhaseCnt==5'h1) begin
				LBDT<=LTDt1[30:15];
				RBDT<=RTDt1[30:15];	
			end		
			else if(PhaseCnt==5'h10) begin
				LBDT<=LBD1;
				RBDT<=RBD1;
			end
			
			if(PhaseCnt[3:0]==4'hf) begin
				Buf2P<=Buf2P+4'b1;
				we2<=1'b1;
			end
			else begin
				we2<=1'b0;
			end
			if(PhaseCnt[3:0]==4'h1)	begin			
				LTDt2<=(LBD2)*wcof2;
				RTDt2<=(RBD2)*wcof2;
			end
			else begin
				LTDt2<=LTDt2+(LBD2)*wcof2;
				RTDt2<=RTDt2+(RBD2)*wcof2;
			end
			if(PhaseCnt[3:0]==4'h1)		begin		
				LDoutBuf<=LTDt2[30:15];
				RDoutBuf<=RTDt2[30:15];	
			end
			else if(PhaseCnt[3:0]==4'h8) begin
				LDoutBuf<=LBD2;
				RDoutBuf<=RBD2;	
			end
			DOutclk<=PhaseCnt[2];
		end
end
always@(posedge DOutclk) begin
	LDout<=LDoutBuf;
	RDout<=RDoutBuf;
end
HBFirCof_1 cof_1(.clk(sysClk),.Address(PhaseCnt[4]?PhaseCnt[3:0]:~PhaseCnt[3:0]),.Data(wcof1));
HBFirCof_2 cof_2(.clk(sysClk),.Address(PhaseCnt[3]?PhaseCnt[2:0]:~PhaseCnt[2:0]),.Data(wcof2));
ram_Buff1 Buff1L(.q(LBD1), .a(Addr1), .d(LDin), .we(DInclk), .clk(sysClk));
ram_Buff1 Buff1R(.q(RBD1), .a(Addr1), .d(RDin), .we(DInclk), .clk(sysClk));
ram_Buff2 Buff2L(.q(LBD2), .a(Addr2), .d(LBDT), .we(we2), .clk(sysClk));
ram_Buff2 Buff2R(.q(RBD2), .a(Addr2), .d(RBDT), .we(we2), .clk(sysClk));
endmodule

module ram_Buff1 (q, a, d, we, clk);
output [15:0] q;
input [15:0] d;
input [4:0] a;
input we, clk;
reg [15:0] q;
reg [4:0] read_add;
reg [15:0] mem [31:0];
always @ (posedge clk) begin
	if (we)
		mem[a] <= d;
	q <= mem[a];
	end
endmodule

module ram_Buff2 (q, a, d, we, clk);
output [15:0] q;
input [15:0] d;
input [3:0] a;
input we, clk;
reg [15:0] q;
reg [3:0] read_add;
reg [15:0] mem [15:0];
always @ (posedge clk) begin
	if (we)
		mem[a] <= d;
	q <= mem[a];
	end
endmodule