cicsilu.v

一种基于LUT的预失真方法。其中的一部分

module CICsilu(RST,Sysclk,DInEn,LDi,RDi,DOutEn,LDo,RDo);

parameter ORDER=4; //order of CIC
parameter UP_POWER=1; //up_sample_times=2^UP_POWER
parameter BIT_WIDTH=16; //input and output word width
parameter OUTPUT_DATA_CLOCK=1; //output data occupy clock number.
parameter CNT_WIDTH=1; //2^CNT_WIDTH>=OUTPUT_DATA_CLOCK

input RST,Sysclk,DInEn;
input[BIT_WIDTH-1:0] LDi,RDi;
output DOutEn;
output[BIT_WIDTH-1:0] LDo,RDo;
reg DOutEn;
reg[BIT_WIDTH-1:0] LDo,RDo;

reg[BIT_WIDTH+UP_POWER*(ORDER-1)-1:0] iI[ORDER-1:0],iQ[ORDER-1:0];
reg[BIT_WIDTH+UP_POWER*(ORDER-1)-1:0] cI[ORDER-1:0],cQ[ORDER-1:0];
reg[BIT_WIDTH+UP_POWER*(ORDER-1)-1:0] cId[ORDER-2:0],cQd[ORDER-2:0];	

reg OldLclk,load;
integer m;
reg[CNT_WIDTH-1:0] k;

always@(posedge Sysclk or posedge RST) begin : Comb
	if(RST) begin
		for(m=0;m<ORDER;m=m+1) begin
			cI[m]<=0;cQ[m]<=0;
		end
		for(m=0;m<ORDER-1;m=m+1) begin
			cId[m]<=0;cQd[m]<=0;
		end
		iI[0]<=0;iQ[0]<=0;
		OldLclk<=1'b1;
		load<=DInEn;
	end
	else begin
		if(load) begin
			cI[0]<={{UP_POWER*(ORDER-1){LDi[BIT_WIDTH-1]}},LDi}; 
			cQ[0]<={{UP_POWER*(ORDER-1){RDi[BIT_WIDTH-1]}},RDi}; 
			for(m=0;m<ORDER-1;m=m+1) begin
				cI[m+1]<=cI[m]-cId[m];
				cQ[m+1]<=cQ[m]-cQd[m];
				cId[m]<=cI[m];
				cQd[m]<=cQ[m];			
			end
			iI[0]<=cI[ORDER-1];iQ[0]<=cQ[ORDER-1]; 
		end
		OldLclk<=DInEn;
		load<=(OldLclk==1)&&(DInEn==0);
	end
end

always@(posedge Sysclk or posedge RST) begin:Integerator
	if(RST==1) begin
		for(m=1;m<ORDER;m=m+1) begin
			iI[m]<=0;iQ[m]<=0;
		end
		k<=0;
		DOutEn<=1'b0;
	end
	else begin
		if(k==(OUTPUT_DATA_CLOCK-1)) begin
			for(m=1;m<ORDER;m=m+1) begin
				iI[m]<=iI[m]+iI[m-1];
				iQ[m]<=iQ[m]+iQ[m-1];
			end
			LDo <=iI[ORDER-1][BIT_WIDTH+UP_POWER*(ORDER-1)-1:UP_POWER*(ORDER-1)]; 
			RDo <=iQ[ORDER-1][BIT_WIDTH+UP_POWER*(ORDER-1)-1:UP_POWER*(ORDER-1)]; 
			k<=0;DOutEn<=1'b1;
		end
		else begin
			k<=k+1'b1;
			DOutEn<=1'b0;
		end
	end	
end
endmodule